PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Register (38)
7
6
5
4
3
2
1
0
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Reg
Bit
Name
Description
Luma grab, 8 msbs. Top 8 bits of the "grabbed" luma data after YPROC
38
7-0
Y
9-2
Register (39)
7
6
5
4
3
2
1
0
M
9
M
8
M
7
M
6
M
5
M
4
M
3
M
2
Reg
Bit
Name
Description
39
7-0
M
Msync grab, 8 msbs. Top 8 bits of the "grabbed" mixed sync data after
9-2
YPROC
Register (3A)
7
6
5
4
3
2
1
0
U
9
U
8
U
7
U
6
U
5
U
4
U
3
U
2
Reg
Bit
Name
Description
U grab, 8 msbs. Top 8 bits of the "grabbed" U data
3A
7-0
U
9-2
Register (3B)
7
6
5
4
3
2
1
0
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
Reg
Bit
Name
Description
V grab, 8 msbs. Top 8 bits of the "grabbed" V data
3B
7-0
V
9-2
Register (3C)
7
6
5
4
3
2
1
0
Y
1
Y
0
M
1
M
0
U
1
U
0
V
1
V
0
Reg
3C
3C
3C
3C
Bit
7-6
5-4
3-2
1-0
Name
Description
Luma grab, 2 lsbs. Bottom 2 bits of luma data
Y
1-0
M
Msync grab, 2 lsbs. Bottom 2 bits of mixed sync data
U grab, 2 lsbs. Bottom 2 bits of U data
1-0
1-0
1-0
U
V
V grab, 2 lsbs. Bottom 2 bits of V data
REV. 1.0.0 2/4/03
35
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
