PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Normalized Subcarrier Frequency (24)
7
6
5
4
3
2
1
0
CLMPEN
PFLTEN
CLPSEL
1-0
CLPBY
CLPOF
2-0
Reg
Bit
Name
Description
24
7
DREFSEL
Decoder Reference Signal Select. When HIGH, enables a negative going
clamp pulse on the DREF pin. The position of the clamp pulse is controlled
by register 24. When LOW the DREF pin is HIGH during the active video
portion of each line and LOW during the horizontal and vertical blanking
intervals.
24
24
6
PFLTBY
Phase error filter bypass. When HIGH, no filtering is done on the phase
error signals for the comb filter adapter. When LOW, the filter is enabled.
5-4
CLPSEL
Internal black level clamp selection.
1-0
CLMP[1:0]
Function
00
01
10
Clamp disabled, black level set to 240
Clamp disabled, black level set to 256
Clamp enabled, use Delayed VIDEOB input as
reference
11
Clamp enabled, use LPF as reference
24
24
3
VCLPEN
BAND
Vertical clamp filter enable. When LOW, vertical clamp filter is disabled.
When HIGH, vertical clamp filter is enabled.
2-0
Clamp guard band. When an error value between two consecutive lines
black level is less than the guard band, it does not effect the filtered black
level.
2-0
BANDS[2:0]
000
Function
No guard band
error value < 2
error value < 4
error value < 6
error value < 8
error value < 10
error value < 12
error value < 15
001
010
011
100
101
110
111
Normalized Subcarrier Frequency (25)
7
6
5
4
3
2
1
0
CPDLY
7-0
Reg
Bit
Name
Description
25
7-0
CPDLY
Clamp pulse delay. Controls the number of clock cycles from hsync before
the 0.5 µSec clamp pulse is output to the AVOUT pin. This option is only
enabled when register 24 bit 7 is set HIGH.
7-0
REV. 1.0.0 2/4/03
29
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
