TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 0 (17) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SG0
SG0
SG0
SG0
SG0
SG0
SG0
SG0
0
7
6
5
4
3
2
1
Reg
17
Bit
Name
SG0
Description
7-0
Msync gain, 8 lsbs. Bottom 8 bits of mixed sync scalar
7-0
lsb = 1/256
Buffered register set 0 (18) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG0
YG0
YG0
YG0
YG0
YG0
YG0
YG0
0
7
6
5
4
3
2
1
Reg
18
Bit
Name
YG0
Description
7-0
Y gain, 8 lsbs. Bottom 8 bits of the luma gain
7-0
lsb = 1/256
Buffered register set 0 (19) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
UG0
UG0
UG0
UG0
UG0
UG0
UG0
UG0
7
6
5
4
3
2
1
1
9
0
0
8
Reg
19
Bit
Name
UG0
Description
7-0
U gain, 8 lsbs. Bottom 8 bits of the U gain
lsb = 1/256
7-0
Buffered register set 0 (1A) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
VG0
VG0
VG0
VG0
VG0
VG0
2
VG0
VG0
7
6
5
4
3
Reg
1A
Bit
Name
VG0
Description
7-0
V gain, 8 lsbs. Bottom 8 bits of the V gain
lsb = 1/256
7-0
Buffered register set 0 (1B) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG0
YG0
UG0
UG0
UG0
8
Reserved
VG0
VG0
9
8
10
9
Reg
Bit
7-6
5-3
2
Name
Description
1B
1B
1B
1B
YG0
UG0
Y gain, 2 msb. Top 2 bits of the Y gain. msb = 2
U gain, 3 msbs. Top 3 bits of the U gain. msb = 4
Reserved, set to zero.
9-8
10-8
Reserved
VG0
1-0
V gain, 2 msbs. Top 2 bits of the V gain. msb = 2
9-8
26
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
