PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Comb Filter Control (0F)
7
6
5
4
3
2
1
0
Reserved
CAT
DCES
IPCF
YCCOMP
SYNC
Reg
Bit
Name
Description
0F
0F
7
Reserved
CAT
Reserved, set to zero.
Adaption threshold. Fixes threshold at which different comb filters are selected.
6-5
0
0
1
1
0
1
0
1
5% of max error
15% of max error
25% of max error
50% of max error
0F
4
DCES
D1 C C error signal. When set LOW for D1 chroma comb filters:
B R
a) In 3 line comb filter architectures, the magnitude error between the component
data for that pixel selects the 3 line comb or adapts to a
2 line comb. On a “C pixel” the error signal selected on pixel (x+4) is sent to
B
the XLUT with the magnitude difference between “C pixels” on the same pair
R
of lines, but from pixel (x+3). Likewise on a “C pixel” the error signal selected
R
on pixel (x+5) is sent to the XLUT with the magnitude difference between “C
pixels” on the same lines but from pixel (x+4).
B
b) In 2 line comb filters the magnitude differences between the same pair of lines
is always sent to the XLUT, On a “C pixel” the error from the preceding “C
B
R
pixel” is used and on a “C pixel” the preceding “C pixel” would be used.
R
B
When set HIGH for D1 chroma filters:
This is used for 3 line comb filter architecture that are inhibited from adapting to 2
line comb filter architectures. The input to the XLUT is the magnitude error in C
R
between (0H & 1H) and (1H & 2H) on “C pixels” and the magnitude error
R
between (0H & 1H) and (1H & 2H) on “C pixels”.
B
0F
3-2
IPCF
Comb filter input select. Selects primary inputs to the comb filter.
IPCF
Function
0 0
0 1
1 0
1 1
Flat video
LPF output
HPF output
Reserved
0F
0F
1
0
YCCOMP
SYNC
YC or Composite input select. Selects YC inputs when HIGH and composite
inputs when LOW.
Sync processor select. The syncs are obtained by a LPF when HIGH and by the
comb filter when LOW.
Sync Pulse Generator (10)
7
6
5
4
3
2
1
0
STS
STS
STS
STS
STS
STS
STS
STS
0
7
6
5
4
3
2
1
Reg
10
Bit
Name
STS
Description
7-0
Sync to sync 8 lsbs. Bottom 8 bits of the number of pixels between sync
7-0
pulses.
REV. 1.0.0 2/4/03
23
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
