Data Sheet
differential shunt capacitor at the chip side of the resistors
may be used to provide dynamic charging currents and
may improve performance. The resistors form a low pass
filter with the capacitor, and values must therefore be
determined by requirements for the application.
Therory of Operation
The CDK8307 is an 8-channel, high-speed, CMOS ADC.
The 13-bits given out by each channel are serialized to
12, 13 or 14-bits and sent out on a single pair of pins in
LVDS format. All eight channels of the CDK8307 operate
from a single differential or single ended clock. The sam-
pling clocks for each of the eight channels are generated
from the clock input using a carefully matched clock buf-
fer tree. The 12x/13x/14x clock required for the serializer
is generated internally from FCLK using a phase-locked
loop (PLL). A 6x/6.5x/7x and 1x clock are also output in
LVDS format, along with the data to enable easy data
capture.TheCDK8307usesinternallygeneratedreferences
that can be shorted across several devices to improve
gain-matching. The differential reference value is 1V. This
results in a differential input of -1V to correspond to the
zero code of the ADC, and a differential input of +1V to
correspond to the full-scale code (code 8191).
Figure 9. Input Configuration Diagram
DC-Coupling
Figure 10 shows a recommended configuration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The ADC employs a pipelined converter architecture.
Each stage feeds its output data into the digital error
correction logic, ensuring excellent differential linearity
and no missing codes at 13-bit level.
The CDK8307 operates from two sets of supplies and
grounds. The analog supply and ground set is identified
as AVDD and AVSS, while the digital set is identified by
DVDD and DVSS.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK8307
input specifications.
Recommended Usage
Analog Input
The analog input to the CDK8307 is a switched capacitor
track-and-hold amplifier optimized for differential opera-
tion. Operation at common mode voltages at mid supply
is recommended even if performance will be good for the
ranges specified. The VCM pin provides a voltage suitable
as common mode voltage reference. The internal buffer
for the VCM voltage can be switched off, and driving
capabilities can be changed programming the ext_vcm_
bc<1:0> register.
Detailed configuration and usage instructions must be
found in the documentation of the selected driver, and
the values given in Figure 10 must be varied according to
the recommendations for the driver.
43Ω
33pF
43Ω
Figure 9 shows a simplified drawing of the input network.
The signal source must have sufficiently low output
impedance to charge the sampling capacitors within one
clock cycle. A small external resistor (e.g. 22Ω) in series
with each input is recommended as it helps reducing
transient currents and dampens ringing behavior. A small
Figure 10. DC-Coupled Input
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