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ADS1602IPFBT 参数 Datasheet PDF下载

ADS1602IPFBT图片预览
型号: ADS1602IPFBT
PDF下载: 下载PDF文件 查看货源
内容描述: 16位2.5MSPS模拟数字转换器 [16-Bit, 2.5MSPS Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 26 页 / 395 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ꢉ ꢃꢠ ꢡꢢ ꢣꢤ  
www.ti.com  
SBAS341B − DECEMBER 2004 − REVISED APRIL 2005  
INITIALIZING THE ADS1602  
STEP RESPONSE  
After the power supplies have stabilized, you must  
initialize the ADS1602 by issuing a SYNC pulse as shown  
in Figure 1. This operation needs only to be done once  
after power-up and does not need to be performed when  
exiting the Power-Down mode.  
Figure 47 plots the normalized step response for an input  
applied at t = 0. The x-axis units of time are conversions  
cycles. It takes 51 cycles to fully settle; for fCLK = 40MHz,  
this corresponds to 20.4µs.  
SYNCHRONIZING MULTIPLE ADS1602s  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
The SYNC input can be used to synchronize multiple  
ADS1602s to provide simultaneous sampling. All devices  
to be synchronized must use a common CLK input. With  
the CLK inputs running, pulse SYNC on the falling edge of  
CLK, as shown in Figure 46. Afterwards, the converters  
will be converting synchronously with the FSO outputs  
updating simultaneously. After synchronization, FSO is  
held low until the digital filter has fully settled.  
0.2  
ADS16021  
0
10  
20  
30  
40  
50  
SYNC  
CLK  
SYNC  
CLK  
FSO  
FSO1  
Time (Conversion Cycles)  
DOUT  
DOUT1  
Figure 47. Step Response  
ADS16022  
SYNC  
CLK  
FSO  
FSO2  
DOUT  
DOUT2  
CLK  
SYNC  
FSO1  
FSO2  
...  
...  
tSTL  
Figure 46. Synchronizing Multiple Converters  
19  
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