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SBAS341B − DECEMBER 2004 − REVISED APRIL 2005
CLOCK INPUT (CLK)
DATA FORMAT
The ADS1602 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with any
high-speed data converter, a high quality clock is essential
for optimum performance. Crystal clock oscillators are the
recommended CLK source; other sources, such as
frequency synthesizers, are usually inadequate. Make
sure to avoid excess ringing on the CLK input; keeping the
trace as short as possible will help.
The 16-bit output data is in binary two’s complement
format as shown in Table 2. When the input is positive
out-of-range, exceeding the positive full-scale value of
V
REF, the output clips to all 7FFFh and the OTR output
goes high.
Likewise, when the input is negative out-of-range by going
below the negative full-scale value of –VREF, the output
clips to 8000h and the OTR output goes high. The OTR
remains high while the input signal is out-of-range.
Measuring high-frequency, large amplitude signals
requires tight control of clock jitter. The uncertainty during
sampling of the input from clock jitter limits the maximum
achievable SNR. This effect becomes more pronounced
with higher frequency and larger magnitude inputs.
Fortunately, the ADS1602 oversampling topology reduces
clock jitter sensitivity over that of Nyquist rate converters
such as pipeline and successive approximation
Table 2. Output Code Versus Input Signal
INPUT SIGNAL
(INP – INN)
IDEAL OUTPUT
(1)
CODE
OTR
≥ +V
(> 0dB)
(0dB)
7FFFh
7FFFh
0001h
1
0
0
REF
V
REF
+VREF
Ǹ
converters by a factor of 16.
2
15 * 1
In order to not limit the ADS1602 SNR performance, keep
the jitter on the clock source below the values shown in
Table 1. When measuring lower frequency and lower
amplitude inputs, more CLK jitter can be tolerated. In
determining the allowable clock source jitter, select the
worst-case input (highest frequency, largest amplitude)
that will be seen in the application.
0
0000h
FFFFh
0
0
−VREF
15 * 1
2
8000h
8000h
0
1
215
215 * 1
ǒ
Ǔ
−VREF
215
ǒ
Ǔ
v −VREF
215 * 1
Table 1. Maximum Allowable Clock Source Jitter
for Different Input Signal Frequencies and
Amplitude
(1)
Excludes effects of noise, INL, offset and gain errors.
OUT-OF-RANGE INDICATION (OTR)
MAXIMUM
ALLOWABLE
CLOCK SOURCE
JITTER
INPUT SIGNAL
If the output code exceeds the positive or negative
full-scale, the out-of-range digital output OTR will go high
on the falling edge of SCLK. When the output code returns
within the full-scale range, OTR returns low on the falling
edge of SCLK.
MAXIMUM
MAXIMUM
FREQUENCY
AMPLITUDE
1MHz
1MHz
−2dB
−20dB
−2dB
3.8ps
28ps
7.6ps
57ps
38ps
285ps
500kHz
500kHz
100kHz
100kHz
DATA RETRIEVAL
−20dB
−2dB
Data retrieval is controlled through a simple serial
interface. The interface operates in a master fashion by
outputting both a frame sync indicator (FSO) and a serial
clock (SCLK). Complementary outputs are provided for
the frame sync output (FSO), serial clock (SCLK) and data
output (DOUT). When not needed, leave the
complementary outputs unconnected.
−20dB
18
BB [ BURR-BROWN CORPORATION ]
