ꢉꢃ ꢠꢡ ꢢ ꢣ ꢤ
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SBAS341B − DECEMBER 2004 − REVISED APRIL 2005
FREQUENCY RESPONSE
0.5
0
The linear phase FIR digital filter sets the overall frequency
response. Figure 48 shows the frequency response from
dc to 20MHz for fCLK = 40MHz. The frequency response
of the ADS1602 filter scales directly with CLK frequency.
For example, if the CLK frequency is decreased by half (to
20MHz), the values on the X-axis in Figure 48 would need
to be scaled by half, with the span becoming dc to 10MHz.
fCLK = 40MHz
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0.5
1.0
1.5
2.0
2.5
3.0
3.5
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Figure 49 shows the passband ripple from dc to 1200kHz
(fCLK = 40MHz). Figure 50 shows a closer view of the
passband transition by plotting the response from 900kHz
to 1300kHz (fCLK = 40MHz).
800
900
1000
1100
1200
1300
Frequency (kHz)
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fCLK = 40MHz
Figure 50. Passband Transition
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20
40
60
80
ANTI−ALIAS REQUIREMENTS
Higher frequency, out-of-band signals must be eliminated
to prevent aliasing with ADCs. Fortunately, the ADS1602
on-chip digital filter greatly simples this filtering
requirement. Figure 51 shows the ADS1602 response out
to 120MHz (fCLK = 40MHz). Since the stop band extends
out to 38.6MHz, the anti-alias filter in front of the ADS1602
only needs to be designed to remove higher frequency
signals than this, which can usually be accomplished with
a simple RC circuit on the input driver.
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100
120
140
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10 12
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Frequency (MHz)
Figure 48. Frequency Response
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fCLK = 40MHz
0.001
0.0008
0.0006
0.0004
0.0002
0
0
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20
40
60
80
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0.0002
0.0004
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100
120
140
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−0.0006
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0.0008
fCLK = 40MHz
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0.001
0
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40
60
80
100
120
0
200
400
600
800
1000
1200
Frequency (MHz)
Frequency (kHz)
Figure 51. Frequency Response Out to 120MHz
Figure 49. Passband Ripple
20
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