A simple two-wire interface is shown in Figure 15. Essentially
P3.2 (INT0) generates an internal interrupt when DOUT/
DRDY pulses LOW. The user firmware in the 8xC51 vectors
to the interupt handler and shifts the data in using P3.1 as
SCLK and P3.2 as data in. The P1.0 output from 8xC51 is a
free-running clock.
ISOLATION
The serial interface of the ADS1252 provides for simple
isolation methods. An example of an isolated three-wire
interface is shown in Figure 16. The ISO150 is used to
transmit the digital clocks over the isolation barrier. In
addition, the digital output of the ADS1252 can, in some
cases, drive opto-isolators directly.
The data must be clocked out before the ADS1252 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
DVDD
8xC51
P1.0/T2
P1.1
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
P1.2
P1.3
P1.4
VREF
Circuit
P1.5
P1.6
P1.7
RST
+VIN
–VIN
+VDD
CLK
VREF
GND
VS
P3.0
ADS1252
P3.1
ALE
SCLK
P3.2 (INT0)
P3.3
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DOUT/DRDY
P3.4
P3.5
P3.6
P3.7
C1
C2
XTAL
XTAL2
XTAL1
VSS
DGND
FIGURE 15. Two-Wire Interface to an 8xC51.
®
ADS1252
12
BB [ BURR-BROWN CORPORATION ]
