+5V
+5V
0.10µF
7
4.99kΩ
2
3
To VREF
Pin 8 of
6
OPA350
10kΩ
the ADS1252
1
+
10µF
0.1µF
+
10µF
0.10µF
4
LM404-4.1
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the ADS1252.
REFERENCE INPUT
For 50Hz rejection, the system CLK frequency should be
19.200kHz, this will set the data output rate to 50Hz (see
Table I and Figure 4). For 60Hz rejection, the system CLK
frequency should be 20.040kHz, this will set the data output
rate to 60Hz (see Table I and Figure 5). If both 50Hz and
60Hz rejection is required, then the system CLK should be
3.840kHz; this will set the data output rate to 10Hz and
reject both 50Hz and 60Hz (See Table I and Figure 6).
Reference input takes an average current of 220µA with a
16MHz system clock. This current will be proportional to
the system clock. A buffered reference is needed for
ADS1252. The recommended reference circuit is shown in
Figure 2.
Reference voltages higher than 4.096V will increase the
full-scale range, while the absolute internal circuit noise of
the converter remains the same. This will decrease the noise
in terms of ppm of full scale, which increases the effective
resolution.
There is an additional benefit in using a lower data output
rate. It provides better rejection of signals in the frequency
band of interest. For example, with a 50Hz data output rate,
a significant signal at 75Hz may alias back into the passband
at 25Hz. This is due to the fact that rejection at 75Hz may
only be 66dB in the stopband—frequencies higher than the
first notch frequency (see Figure 4). However, setting the
data output rate to 10Hz will provide 135 dB rejection at
75Hz (see Figure 6). A similar benefit is gained at frequen-
cies near the data output rate (see Figures 7, 8, 9, and 10).
For example, with a 50Hz data output rate, rejection at 55Hz
may only be 105dB (see Figure 7). However, with a 10Hz
data output rate, rejection at 55Hz will be 122dB (see Figure
8). If a slower data output rate does not meet the system
requirements, then the analog front end can be designed to
provide the needed attenuation to prevent aliasing. Addition-
ally the data output rate may be increased and additional
digital filtering may be done in the processor or controller.
Reference voltages lower than 4.096V will decrease the full-
scale range, while the absolute internal circuit noise at the
converter remains the same. This will increase the noise in
terms of ppm of full scale. Therefore, the use of a lower
reference voltage will reduce the effective resolution.
DIGITAL FILTER
The digital filter of the ADS1252, referred to as a sinc5 filter,
computes the digital result based on the most recent outputs
from the delta-sigma modulator. At the most basic level, the
digital filter can be thought of as simply averaging the
modulator results in a weighted form and presenting this
average as the digital output. The digital output rate, or data
rate, scales directly with the system CLK frequency. This
allows the data output rate to be changed over a very wide
range (five orders of magnitude) by changing the system
CLK frequency. However, it is important to note that the
–3dB point of the filter is 0.216 times the data output rate,
so the data output rate should allow for sufficient margin to
prevent attenuation of the signal of interest.
The digital filter is described by the following transfer
function:
5
π • f • 64
sin
fMOD
H(f) =
π • f
64 •sin
Since the conversion result is essentially an average, the data
output rate determines the location of the resulting notches
in the digital filter (see Figure 3). Note that the first notch is
located at the data output rate frequency, and subsequent
notches are located at integer multiples of the data output
rate to allow for rejection of not only the fundamental
frequency, but also harmonic frequencies. In this manner,
the data output rate can be used to set specific notch
frequencies in the digital filter response. For example, if the
rejection of power line frequencies is desired, then the data
output rate can simply be set to the power line frequency.
fMOD
or
5
1 – z–64
H(z) =
64 • 1– z–1
(
)
The digital filter requires five conversions to fully settle. The
modulator has an oversampling ratio of 64, therefore, it
requires 5 • 64, or 320 modulator results, or clocks, to fully
settle. Since the modulator clock is derived from the system
®
7
ADS1252
BB [ BURR-BROWN CORPORATION ]
