DRDY Mode
t4
DRDY Mode
DOUT Mode
DOUT Mode
t2
t3
DATA
DATA
DATA
DOUT/DRDY
t1
FIGURE 11. DOUT/DRDY Partitioning.
to DOUT mode. Data would be shifted out on the pin after
t7. The device communicating with the ADS1252 can pro-
vide SCLKs to the ADS1252 after the time defined by t6.
The normal mode of reading data from the ADS1252 would
be for the device reading the ADS1252 to latch the data on
the rising edge of SCLK (since data is shifted out of the
ADS1252 on the falling edge of SCLK). In order to retrieve
valid data, the entire DOR must be read before the
DOUT/DRDY pin reverts back to DRDY mode.
POWER-DOWN MODE
The normal state of SCLK is LOW. However, by holding
SCLK HIGH, the ADS1252 will enter power-down mode.
This is accomplished by holding SCLK HIGH for at least
twenty consecutive DOUT/DRDY periods (see Figure 14).
After the ADS1252 circuitry detects that SCLK has been
held HIGH for four consecutive DOUT/DRDY cycles, the
DOUT/DRDY pin will pulse LOW for 3 CLK cycles and
then be held HIGH, and the modulator will be held in a reset
state. If SCLK is held HIGH for an additional sixteen
DOUT/DRDY periods, the ADS1252 will enter power-
down mode. The part will be released from power-down
mode on the falling edge of SCLK. It is important to note
that the DOUT/DRDY pin will be held HIGH after four
DOUT/DRDY cycles, but power-down mode will not be
entered for an additional sixteen DOUT/DRDY periods. The
first DOUT/DRDY pulse after the falling edge of SCLK will
occur at t16. Subsequent DOUT/DRDY pulses will occur
normally. Valid data will not be present until the sixth
DOUT/DRDY pulse.
If SCLKs were not provided to the ADS1252 during the
DOUT mode, the MSB of the DOR would be present on the
DOUT/DRDY line until the time defined by t4. If an incom-
plete read of the ADS1252 took place while in DOUT mode
(i.e., less than 24 SCLKs were provided), the state of the last
bit read would be present on the DOUT/DRDY line until the
time defined by t4. If more than 24 SCLKs were provided
during DOUT mode, the DOUT/DRDY line would stay
LOW until the time defined by t4.
The internal data pointer for shifting data out on
DOUT/DRDY is reset on the falling edge of the time defined
by t1 and t4. This ensures that the first bit of data shifted out
of the ADS1252 after DRDY mode is always the MSB of
new data.
SERIAL INTERFACE
The ADS1252 includes a simple serial interface which can
be connected to microcontrollers and digital signal proces-
sors in a variety of ways. Communications with the ADS1252
can commence on the first detection of the DOUT/DRDY
pulse after power up, although data will not be valid until the
sixth conversion.
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW. However, by holding
SCLK HIGH, multiple ADS1252s can be synchronized.
This is accomplished by holding SCLK HIGH for at least
four, but less than twenty, consecutive DOUT/DRDY cycles
(see Figure 13). After the ADS1252 circuitry detects that
SCLK has been held HIGH for four consecutive
DOUT/DRDY cycles, the DOUT/DRDY pin will pulse
LOW for 3 CLK cycles and then be held HIGH, and the
modulator will be held in a reset state. The modulator will be
released from reset and synchronization will occur on the
falling edge of SCLK. It is important to note that prior to
synchronization, the DOUT/DRDY pulse of multiple
ADS1252s in the system could have a difference in timing
up to one DRDY period. Therefore to ensure synchroniza-
tion, the SCLK should be held HIGH for at least five DRDY
cycles. The first DOUT/DRDY pulse after the falling edge
of SCLK will occur at t14. Valid data will not be present until
the sixth DOUT/DRDY pulse.
It is important to note that the data from the ADS1252 is a
24-bit result transmitted MSB-first in Offset Two’s Comple-
ment format, as shown in Table III.
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Fulll Scale
Zero
7FFFFFH
000000H
800000H
–Full Scale
TABLE III. ADS1252 Data Format (Offset Two's Comple-
ment).
®
ADS1252
10
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