magnitude of the effect is dependent on the desired system
performance.
THEORY OF OPERATION
The ADS1252 is a precision, high dynamic range, 24-bit,
delta-sigma, A/D converter capable of achieving very high-
resolution digital results at high data rates. The analog input
signal is sampled at a rate determined by the frequency of
the system clock (CLK). The sampled analog input is modu-
lated by the delta-sigma A/D modulator. This is followed by
a digital filter. A sinc5 digital low-pass filter processes the
output of the delta-sigma modulator and writes the result
into the data output register. The DOUT/DRDY pin is pulled
LOW indicating that new data is available to be read by the
external microcontroller/microprocessor. As shown in the
block diagram, the main functional blocks of the ADS1252
are the fourth-order delta-sigma modulator, a digital filter,
control logic, and a serial interface. Each of these functional
blocks is described below.
Second, the current into or out of the analog inputs must be
limited. Under no conditions should the current into or out
of the analog inputs exceed 10mA.
Third, to prevent aliasing of the input signal, the bandwidth
of the analog input signal must be band limited. The band-
width is a function of the system clock frequency. With a
system clock frequency of 16MHz, the data output rate is
41.667kHz, with a –3dB frequency of 9kHz. The –3dB
frequency scales with the system clock frequency.
To guarantee the best linearity of the ADS1252, a fully
differential signal is recommended.
DELTA-SIGMA MODULATOR
The ADS1252 operates from a nominal system clock fre-
quency of 16MHz. The modulator frequency is fixed in
relation to the system clock frequency. The system clock
frequency is divided by 6 to derive the modulator frequency.
Therefore, with a system clock frequency of 16MHz, the
modulator frequency is 2.667MHz. Furthermore, the
oversampling ratio of the modulator is fixed in relation to the
modulator frequency. The oversampling ratio of the modu-
lator is 64, and with the modulator frequency running at
2.667MHz, the data rate is 41.667kHz. Using a slower
system clock frequency will result in a lower data output
rate, as shown in Table I.
ANALOG INPUT
The ADS1252 contains a fully differential analog input. In
order to provide low system noise, common-mode rejection
of 100dB, and excellent power supply rejection, the design
topology is based on a fully differential switched-capacitor
architecture. The bipolar input voltage range is from –4.096
to +4.096V when the reference input voltage equals +4.096V.
The bipolar range is with respect to –VIN and not with
respect to GND.
Figure 1 shows the basic input structure of the ADS1252.
The impedance is directly related to the sampling frequency
of the input capacitor which is set by the CLK rate. Higher
CLK rates result in lower impedance and lower CLK rates
result in higher impedance.
CLK (MHz)
DATA OUTPUT RATE (Hz)
16.000(1)
15.360(1)
41.667
40,000
30,063
38,400
37,287
32,000
31,250
28,800
26,042
25,000
19,200
16,000
15,625
12,800
9,600
8,000
6,400
4,800
2,400
1,200
1,000
500
15.000(1)
14.745600(1)
14.318180(1)
12.288000(1)
12.000000(1)
11.059220(1)
10.000000(1)
9.600000
7.372800(1)
6.144000(1)
6.000000(1)
4.915200(1)
3.686400(1)
3.072000(1)
2.457600(1)
1.843200(1)
0.921600
0.460800
0.384000
0.192000
0.038400
0.023040
0.019200
0.011520
0.009600
0.007680
0.006400
0.005760
0.004800
0.003840
RSW
(300Ω typical)
Internal
Circuitry
AIN
CINT
Modulator Frequency
(20pF typical)
= fMOD
VCM
FIGURE 1. Analog Input Structure.
The input impedance of the analog input changes with
ADS1252 system clock frequency (CLK). The relationship
is:
100
60
50
30
25
20
16.67
15
AIN Impedance (Ω) = (16MHz/CLK) • 19,000
With regard to the analog input signal, the overall analog
performance of the device is affected by three items. First,
the input impedance can affect accuracy. If the source
impedance of the input signal is significant, or if there is
passive filtering prior to the ADS1252, a significant portion
of the signal can be lost across this external impedance. The
12.50
10
NOTE: (1) Standard Clock Oscillator.
TABLE I. CLK Rate versus Data Output Rate.
®
ADS1252
6
BB [ BURR-BROWN CORPORATION ]
