DIGITAL FILTER RESPONSE
DIGITAL FILTER RESPONSE
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
55
56
57
58
59
60
61
62
63
64
65
55
56
57
58
59
60
61
62
63
64
65
Frequency (Hz)
Frequency (Hz)
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz Notch).
FIGURE 10. Expanded Digital Filter Response (60Hz with
a 10Hz Notch).
clock (CLK) (modulator clock = CLK ÷ 6), the number of
system clocks required for the digital filter to fully settle is
5 • 64 • 6, or 1920 CLKs. This means that any significant
step change at the analog input requires five full conversions
to settle. However, if the analog input change occurs asyn-
chronously to the DOUT/DRDY pulse, six conversions are
required to ensure full settling.
DOUT/DRDY
The DOUT/DRDY output signal alternates between two
modes of operation. The first mode of operation is the Data
Ready mode (DRDY) to indicate that new data has been
loaded into the data output register and is ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). The time domain partitioning of the DRDY
and DOUT function is shown in Figure 11.
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1252.
The basic timing for DOUT/DRDY is shown in Figure 12.
During the time defined by t2, t3, and t4, the DOUT/DRDY
pin functions in DRDY mode. The state of the
DOUT/DRDY pin would be HIGH prior to the internal
transfer of new data to the DOR. The result of the A/D
conversion would be written to the DOR from MSB to LSB
in the time defined by t1 (see Figures 11 and 12). The
DOUT/DRDY line would then pulse LOW for the time
defined by t2, and then pulse HIGH for the time defined by
t3 to indicate that new data was available to be read. At this
point, the function of the DOUT/DRDY pin would change
Power-Up Sequence
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed +VD.
Once the ADS1252 powers up, the DOUT/DRDY line will
pulse LOW on the first conversion. This data will not be
valid. The sixth pulse of DOUT/DRDY will be valid data
from the analog input signal.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tDRDY
DRDY Mode
DOUT Mode
Conversion Cycle
DRDY Mode
DOUT Mode
DOR Write Time
384 • CLK
36 • CLK
348 • CLK
6 • CLK
6 • CLK
6 • CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
DOUT/DRDY LOW Time
DOUT/DRDY HIGH Time (Prior to Data Out)
DOUT/DRDY HIGH Time (Prior to Data Ready)
Rising Edge of CLK to Falling Edge of DOUT/DRDY
End of DRDY Mode to Rising Edge of First SCLK
End of DRDY Mode to Data Valid (Propogation Delay)
Falling Edge of SCLK to Data Valid (Hold Time)
Falling Edge of SCLK to Next Data Out Valid (Propogation Delay)
SCLK Setup Time for Synchronization or Power Down
DOUT/DRDY Pulse for Synchronization or Power Down
Rising Edge of SCLK Until Start of Synchronization
Synchronization Time
24 • CLK
30
30
30
30
5
30
3 • CLK
1537 • CLK
0.5 • CLK
7679 • CLK
6143.5 • CLK
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Rising Edge of SCLK Until Start of Power Down
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Falling Edge of Last DOUT/DRDY to Start of Power Down
314.5 • CLK
6143.5 • CLK
7681 • CLK
591.5 • CLK
592.5 • CLK
TABLE II. Digital Timing.
®
9
ADS1252
BB [ BURR-BROWN CORPORATION ]
