Another key issue is the purity of both the signal and
sampling frequency generators. The sampling clock’s phase
noise (jitter) will act as another source of SNR degradation.
This is not serious as long as the jitter is random and the
noise sidebands contain no sharp peaks. The HP3325 syn-
thesizer is suitable for this purpose. The input signal genera-
tor will require more attention because its distortion will
usually be greater than that of the ADC701/SHC702. Pres-
ently, the lowest distortion synthesized generator is the
Brüel & Kjær Model 1051 (or 1049). This is suitable for
testing the system in the audio range. The upper frequency
limit of the B&K synthesizer is 200kHz. Above 20kHz, the
distortion becomes a limiting factor, and low-pass filters
must be inserted into the signal path to reduce the harmonic
and spurious content.
As noted previously, the combined noise contributions of
the signal generator and sampling clock generator far exceed
the SNR of the ADC701/SHC702 itself. The SNR has been
measured separately by applying a highly filtered sinewave
to the input, resulting in typical SNR performance of –93dB.
However, the filters employed to achieve this low-noise test
stimulus are found to cause reactive loading of the signal
source which results in increased distortion. Therefore it is
best to separate the tests for SNR from those for THD and
IMD, unless a suitably pure and low-noise signal can be
generated.
Figures 5 and 6 show block diagrams of FFT test setups for
the ADC701 and SHC702, summarizing the placement of
the major components discussed above. The Typical Dy-
namic Performance section shows typical results obtained
from testing the ADC701/SHC702 at a 500kHz conversion
rate, using 16K samples for the FFT analysis.
Start Conversion
N
Start Conversion
N + 1
ADC701
Convert Command
(CC)
50ns min
50ns min
CC to Hold delay 18ns typ
Hold Mode
1.45µs typ
Hold Command
to SHC702
Sample Mode
Low Byte,(4)
Data N – 1
Low Byte,(4)
Data N
High Byte,(3)
Data N
Data Outputs for
Pin 13 = Low
Data Outputs for
Pin 13 = High
Low Byte,(4)
Data N
High Byte,(3)
Data N – 1
High Byte,(3)
Data N
(2)
(1)
(1)
110ns
typ
Data Strobe Output
1.55µs typ
NOTES: (1) Setup Time 28ns min, 37ns typ. (2) Hold Time 30ns min, 73ns typ. (3) High Byte refers to ADC bits 1 - 8, the most significant 8 bits.
Also, the Clip Detect signal on pin 9 is valid simultaneously with High Byte. (4) Low Byte refers to ADC bits 9 - 16, the least significant bits.
FIGURE 5. FFT Test Configuration for Single-Tone Testing.
®
14
ADC701/SHC702
BB [ BURR-BROWN CORPORATION ]
