OPTIONS FOR STROBED OUTPUT
ADC701 Digital I/O
There are several ways in practice to implement the logic
interface. Figure 3 shows the simplest configurations. In
order to convert the ADC701’s byte-sequential data into 16-
bit parallel form, the minimum requirement is for one single
octal flip-flop, such as a 74HC574 or equivalent. This will
latch the first byte on the rising edge of the ADC701 Data
Strobe. Then the second byte becomes valid, and all 16 bits
may be strobed to the outside system on the falling edge of
the Data Strobe.
Refer to the timing diagram, Figure 4. The conversion
process is initiated by a rising edge on the Convert Com-
mand input. This will immediately bring the sample/hold
command output to a logic high state (Hold mode).
After the ADC701 conversion is completed (approximately
1.5µs after the convert command edge), the Sample/Hold
Command falls to a low state, enabling the sample/hold to
begin acquisition of the next input sample. However, the
ADC701 internal clock continues to run so that the output
data may be processed.
For better noise isolation of the ADC701 from the digital
system, or if full three-state capability is required for the 16
output lines, a second octal flip-flop can be added as shown
in the dashed lines of Figure 3. This will also require an
inverter to convert the falling Data Strobe edge into a rising
clock edge for the second flip-flop IC.
There are two methods of reading data from the ADC:
1. Strobed Output—This will usually be the easiest and
fastest method. The data are presented sequentially as
high and low bytes of the total 16-bit word. The sequence
High-Low or Low-High is controlled by the state of the
High/Low Byte Select input. The first byte is valid on the
rising edge of the Data Strobe output; the second byte is
valid on the falling edge.
If it is desirable to have all 16 output lines change simulta-
neously (for example when driving a D/A converter), then a
third octal flip-flop (not shown in Figure 3) may be added to
re-latch the output of the first byte. By driving that device’s
clock also from the inverted Data Strobe, fully synchronous
switching of the 16 output bits will be achieved.
2. Polled output—With this method, data strobes will occur
as described above, but they are ignored by the user.
Instead, the user waits until the Data Strobe output falls,
and then manually selects high and low output data by
means of the High/Low Byte Select input. This polling
procedure may be carried out during the subsequent ADC
conversion cycle, but two precautions must be observed:
First, the user should avoid switching the High/Low Byte
Select immediately before or after the next convert com-
mand. This will prevent digital switching noise from
coupling into the system at the instant of analog sam-
pling. Second, the polling sequence must be completed
before the ADC begins to strobe out data from the
subsequent conversion.
USING THE CLIP DETECT OUTPUT
The ADC701 provides a built-in Clip Detect signal on pin 9
which indicates an ADC overrange or underrange condition.
The Clip Detect signal is only valid when the High Byte
becomes valid as shown in Figure 4. Therefore, the simplest
way to latch the Clip Detect signal is to provide an extra flip-
flop which is clocked on the same strobe edge as the High
Byte flip-flop. Such a setup is illustrated in Figure 3. The
Clip Detect signal remains at logic 0 under normal condi-
tions, and indicates a clip condition by rising to a logic 1.
Start Conversion
N
Start Conversion
N + 1
ADC701
Convert Command
(CC)
50ns min
50ns min
CC to Hold delay 18ns typ
Hold Mode
1.45µs typ
Hold Command
to SHC702
Sample Mode
Low Byte,(4)
Data N – 1
Low Byte,(4)
Data N
High Byte,(3)
Data N
Data Outputs for
Pin 13 = Low
Data Outputs for
Pin 13 = High
Low Byte,(4)
Data N
High Byte,(3)
Data N – 1
High Byte,(3)
Data N
(2)
(1)
(1)
110ns
typ
Data Strobe Output
1.55µs typ
NOTES: (1) Setup Time 28ns min, 37ns typ. (2) Hold Time 30ns min, 73ns typ. (3) High Byte refers to ADC bits 1 - 8, the most significant 8 bits.
Also, the Clip Detect signal on pin 9 is valid simultaneously with High Byte. (4) Low Byte refers to ADC bits 9 - 16, the least significant bits.
FIGURE 4. ADC701 Interface Timing Diagram.
®
11
ADC701/SHC702
BB [ BURR-BROWN CORPORATION ]
