At the beginning of each conversion, the DAC is reset to
mid-scale so that its output current is exactly 1mA. This
1mA is subtracted from the input signal current. The differ-
ence current flows through Rf and appears as an error
voltage at the output of A1.
INSTALLATION AND
OPERATING INSTRUCTIONS
The ADC701/SHC702 combination is designed to be easy to
use in a wide variety of applications, without sacrificing
flexibility of the analog and digital interface.
During the first pass, the programmable gain amplifier
(PGA) is set to unity gain, which matches the error voltage
range to the input range of the flash ADC. The error signal
is digitized to 7-bit resolution by the flash ADC, creating a
coarse approximation of the digital output value, which is
then applied to the DAC.
SHC702 INTERFACE
The connection diagram (Figure 3) shows the basic hookup.
At the SHC702 input, the user may opt to connect the built-
in FET buffer amplifier. The buffer is most useful in multi-
channel applications where the signal bandwidth is less than
100kHz. In those applications, it serves to isolate the multi-
plexer output from the 1kΩ input impedance of the sample/
hold. For higher frequency applications and for any system
that does not require the very high impedance, the best
results (lowest noise and distortion) will be achieved by
driving the SHC702’s analog input directly. If the buffer is
not used, its input should be grounded to avoid random noise
pickup and saturation of the buffer op amp.
Since the DAC output is now approximately equal to the
input signal current, the remaining difference current flow-
ing through Rf is small—ideally less than 1/128 of full scale,
which is due to the built-in quantizing uncertainty of the 7-
bit flash ADC. However, other sources of error (e.g., integral
and differential nonlinearity of the flash ADC, gain and
offset of the PGA, settling and noise errors throughout the
signal path) cause the possible error range to be significantly
greater. In fact, the ADC701 is designed to handle remainder
signals up to 1/32 of full scale, which is four times the
“ideal” value.
Only two connections are required between the SHC702 and
the ADC701: SHC702 analog output to ADC701 input(s)
and the digital Hold Command from the ADC701 to the
SHC702. As always, it is best to avoid routing these analog
and digital lines along parallel traces. Although the place-
ment of the SHC702 relative to the ADC is not extremely
critical, one good approach is to mount the SHC along one
end of the ADC package as shown in Figure 4. This mini-
mizes the length of the interconnections and keeps the
digital lines well away from sensitive analog signals.
Therefore, the PGA is set during the second pass to a gain
of 32, allowing the small remainder signal to match the full
range of the flash ADC. This is again digitized to 7-bit
resolution and added to the previous result to create the
“medium” approximation of the input signal. Because the
full-scale range of the flash represents 1/32 of the input
signal’s full range, the 7-bit flash output is shifted right by
5 bits before being added to the original 7-bit “coarse”
result, creating a 12-bit word. There is an overlap of two bits
because the two least significant bits of the first-pass result
correspond to the two most significant bits of the second-
pass result. This overlap in the adder is called “digital error
correction”—the mechanism that allows nonideal remain-
ders from the first pass to be corrected in the second pass.
ADC701 INPUT CONNECTIONS
The ADC input network has four separate terminals, allow-
ing many different input ranges. These should be connected
as indicated in Table I. Most users will take advantage of the
ADC701’s built-in reference circuit, which has very low
noise and excellent temperature stability. To use the internal
reference, it is only necessary to connect pin 36 (Reference
Output) to pin 32 (Reference Input). To use an external 10V
reference (to cause the ADC gain to track a system refer-
ence, for example), pin 36 is left unconnected and the
external reference is applied to pin 32. If required, the
ADC701 will typically accommodate a five to ten percent
variation in the 10V reference. External references should
have very low noise to avoid degrading the excellent signal-
to-noise ratio (SNR) of the ADC701.
The 12-bit approximation is applied once again to the DAC,
causing the remaining difference current to become yet
smaller. For the third pass, the PGA’s gain is increased by
another factor of 32, and the remainder is again digitized by
the flash ADC.
At this point in the conversion, all of the necessary data has
been latched and it is no longer necessary to hold the analog
signals from the sample/hold or the DAC. From a systems
perspective, the conversion is now complete because the
sample/hold is released to begin acquiring the next input
sample and the DAC is reset to mid-scale for the next
conversion. Meanwhile, the final result from the flash is
added to the previous 12-bit result. Again there is a two-bit
overlap to allow for error correction. The adder output is
monitored to prevent a digital “rollover” condition, so that
the ADC clips properly at the signal extremes. The upper
sixteen bits of the final adder result are stored in the ADC’s
output register, ready to be presented in byte-sequential
form at the eight output data lines. The overrange or “clip”
condition can also be detected externally by monitoring pin
9. Refer to the section on ADC701 Digital I/O for further
detail.
INPUT RANGE
CONNECT VIN TO
CONNECT Ref In TO
0 to +10V
±10V
Input A and Input D
Input A
—
Input D
Input D
±5V
–10V to 0
0 to +5V
Input A and Input B
Input A and Input B
Input B and Input C
Input C and Input D
—
TABLE I. ADC701 Input Connection Table.
®
8
ADC701/SHC702
BB [ BURR-BROWN CORPORATION ]
