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ADC701JH 参数 Datasheet PDF下载

ADC701JH图片预览
型号: ADC701JH
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 转换器
文件页数/大小: 15 页 / 112 K
品牌: BB [ BURR-BROWN CORPORATION ]
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The ADC701 input voltage is converted to a current through  
the input scaling resistors (Figure 2), and this current is  
applied to the summing junction (virtual ground) of error  
amplifier A1. The current output of the DAC (0 to 2mA) is  
also applied to the summing point. If bipolar operation is  
selected, the 10V reference output is applied to input D,  
creating a 1mA offset current which sums with the input  
current.  
THEORY OF OPERATION  
The ADC701 uses a three-step subranging architecture,  
meaning that the analog-to-digital conversion is performed  
in three passes which constitute coarse, medium and fine  
approximations of the input signal. Refer to Figures 1 and 2  
for simplified block diagrams of the system.  
Before the input signal is presented to the ADC, it must be  
sampled with high linearity and low aperture error by the  
sample/hold amplifier.  
1kΩ  
In the SHC702, the sampling switch is placed at the sum-  
ming junction (virtual ground) of a high speed FET ampli-  
fier (Figure 1). This arrangement maintains constant charge  
injection independent of the signal amplitude, which is  
critically important for good linearity performance. The  
sampling switch itself is a high speed DMOS FET whose  
gate is driven from a fast-slewing control signal, thus mini-  
mizing the time aperture between the fully closed (sample  
mode) and the fully open (hold mode) states of the switch.  
The signal voltage is held across the feedback capacitor,  
forcing the op-amp to maintain a constant output voltage for  
the duration of the A/D conversion. Feedthrough from the  
input, already low due to the MOSFET’s low capacitance, is  
further reduced by clamping the summing point to ground  
with another FET.  
CHOLD  
1kΩ  
Analog  
Input  
+
Analog  
Output  
Hold  
Hold  
Switch and  
Clamp Drive  
Signal  
Conditioning  
FIGURE 1. Simplified Block Diagram of the SHC702.  
Ref Ref Input  
Input  
D
Input  
A
Input  
B
Out In  
C
5kΩ  
5kΩ  
5kΩ  
5kΩ  
Input  
Scaling  
Network  
High Speed PGA  
Attenuator  
Rf  
+
A1  
X32  
X32  
Buffer  
DAC  
Error  
Amp  
10V  
DAC  
Reference  
Register  
PGA Control  
Lines  
VIN  
7 Bit  
Adder  
(Digital Error Correction)  
Flash ADC  
ADC  
Timing and  
Output Register  
Control Logic  
Flash ADC  
Reference  
Generator  
ADC  
Output  
Convert  
Command  
Hold  
Command  
Data  
Strobe  
FIGURE 2. Simplified Block Diagram of the ADC701.  
®
7
ADC701/SHC702