Arizona Microtek, Inc.
AZP63
Low Phase Noise Sine Wave CMOS
to LVPECL Buffer/Translator
OUTPUT TERMINATION TECHNIQUES
The LVPECL compatible output stage of the AZP63 uses a current drive topology to maximize switching speed as
illustrated below in Figure 4. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS
current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output
current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output
voltage swings match LVPECL levels when external 50Ω resistors terminate the outputs.
Both Q and Q¯ should always be terminated identically to avoid waveform distortion and circulating current caused by
unsymmetrical loads. This rule should be followed even if only one output is in use.
VDD (+3.3 V)
Output
Stage
M1
M2
External
Circuitry
Vbp
21.1mA
21.1mA
Q
Q
21.1mA - High
5.1mA - Low
50Ω
50Ω
M3
M4
D
M5
VTT = VDD - 2.0V
Vbn
16mA
Figure 4 - Typical Output Termination
DUAL SUPPLY LVPECL OUTPUT TERMINATION
The standard LVPECL loads are a pair of 50Ω resistors connected between the outputs and VDD-2.0V (Figure 4). The
resistors provide both the DC and the AC loads, assuming 50Ω interconnect. If an additional supply is available within the
application, a four resistor termination configuration is possible (Figure 5).
www.azmicrotek.com
+1-480-962-5881
5
Request a Sample
Mar 2013, Rev 2.2
AZM [ ARIZONA MICROTEK, INC ]
