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AZP63_13 参数 Datasheet PDF下载

AZP63_13图片预览
型号: AZP63_13
PDF下载: 下载PDF文件 查看货源
内容描述: 低相位噪声正弦波/ CMOS到LVPECL缓冲器/转换器 [Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator]
分类和应用: 转换器
文件页数/大小: 12 页 / 519 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
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Arizona Microtek, Inc.  
AZP63  
Low Phase Noise Sine Wave CMOS  
to LVPECL Buffer/Translator  
EVALUATION BOARD (EBP53)  
Arizona Microtek’s evaluation board EBP53 provides the most convenient way to test and prototype AZP63 series  
circuits. Built for the AZP53Q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. Dual  
supply operation (VDD=+2.0V, VSS=-1.3V) enables direct coupling to 50time domain test equipment (Figure 7).  
VDD (+2.0 V)  
Output  
Stage  
Test  
Equipment  
M1  
M2  
Vbp  
Terminations  
21.1mA  
21.1mA  
Q
Q
21.1mA - High  
5.1mA - Low  
50Ω  
50Ω  
M3  
M4  
D
M5  
Vbn  
16mA  
VSS (-1.3 V)  
Figure 7 - Split Supply LVPECL Output Termination  
AC TERMINATION  
Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 8 below  
shows the AC coupling technique. The 200resistors form the required DC loads, and the 50resistors provide the AC  
termination. The parallel combination of the 200and 50resistors results in a net 40AC load termination. In many  
cases this will work well. If necessary, the 50resistors can be increased to about 56. Alternately, bias tees combined  
with current setting resistors will eliminate the lowered AC load impedance. The 50resistors are typically connected to  
ground but can be connected to the bias level needed by the succeeding stage.  
www.azmicrotek.com  
+1-480-962-5881  
7
Request a Sample  
Mar 2013, Rev 2.2