Arizona Microtek, Inc.
AZP63
Low Phase Noise Sine Wave CMOS
to LVPECL Buffer/Translator
Figure 2- S11, Parameters,D Input
INPUT TERMINATION
TheD input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least
750mVpp ensures the AZP63 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle
on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation.
Input signal
D
10kΩ
A/R
VDD/2
Figure 3 - Input Termination
www.azmicrotek.com
+1-480-962-5881
4
Request a Sample
Mar 2013, Rev 2.2