SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
COMMANDS
Truth Table 1 provides a quick reference of available commands.
This is followed by a written description of each command.
Two additional Truth Tables appear following the Operation
section; these tables provide current state/next state informa-
tion.
TRUTH TABLE 1- Commands and DMQ Operation
(Note: 1)
NAME (FUNCTION)
CS\ RAS\ CAS\ WE\ DQM
ADDR
DQs NOTES
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
H
L
L
L
L
L
L
X
H
L
H
H
H
L
X
H
H
L
L
H
H
X
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
ACTIVE (select bank and activate row)
READ (select bank and column and start READ burst)
WRITE (select bank and column and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (enter self refresh
mode)
Bank/Row
Bank/Col
Bank/Col Valid
X
Code
3
4
4
L
L
Active
X
5
L
L
L
H
X
X
X
6,7
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
L
-
-
L
-
-
L
-
-
L
-
-
X
L
H
OpCode
X
2
8
8
-
-
Active
High-Z
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the Mode Register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10
LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are
“Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
9
AUSTIN [ AUSTIN SEMICONDUCTOR ]
