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AS4SD4M16DG-10/XT 参数 Datasheet PDF下载

AS4SD4M16DG-10/XT图片预览
型号: AS4SD4M16DG-10/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 4梅格×16 SDRAM同步动态随机存取存储 [4 Meg x 16 SDRAM Synchronous DRAM Memory]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 50 页 / 1139 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SDRAM  
AS4SD4M16  
Austin Semiconductor, Inc.  
PIN DESCRIPTION  
TSOP  
PIN NUMBERS  
38  
DESCRIPTION  
SYMBOL TYPE  
CLK  
CKE  
Input Clock: CLK is driven by the system clock. All SDRAM input signals are  
sampled on the positive edge of CLK. CLK also increments the internal burst  
counter and controls the output registers.  
37  
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.  
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF  
REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE  
in either bank) or CLOCK SUSPEND operation (burst/access in progress).  
CKE is synchronous except after the device enters power-down and self  
refresh modes, where CKE becomes asynchronous until after exiting the  
same mode. The input buffers, including CLK, are disabled during power-down  
and self refresh modes, providing low standby power. CKE may be tied  
HIGH.  
19  
CS\  
Input Chip Select: CS\ enables (registered LOW) and disables (registered HIGH)  
the command decoder. All commands are masked when CS\ is registered  
HIGH. CS\ provides for external bank selection on systems with multiple  
banks. CS\ is considered part of the command code.  
16, 17  
18  
WE\, CAS\ Input Command Inputs: RAS\, CAS\, and WE\ (along with CS\) define the  
RAS\  
command being entered.  
15, 39  
DQML,  
DQMH  
Input Input/Output Mask: DQM is an input mask signal for write accesses and an  
output enable signal for read accesses. Input data is masked when DQM is  
sampled HIGH during a WRITE cycle. The output buffers are placed in a  
High-Z state (two-clock latency) when DQM is sampled HIGH during a READ  
cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15.  
DQML and DQMH are considered same state when referenced as DQM.  
20, 21  
BA0, BA1  
A0-A11  
Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ,  
WRITE or PRECHARGE command is being applied.  
23-26, 29-34,  
22, 35  
Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row  
address A0-A11) and READ/WRITE command (column address A0-A7, with  
A10 defining AUTO PRECHARGE) to select one location out of the memory  
array in the respective bank. A10 is sampled during a PRECHARGE  
command to determine if all banks are to be precharged (A10 HIGH) or bank  
selected by BA0,BA1 (LOW). The address inputs also provide the op-code  
during a LOAD MODE REGISTER command.  
2, 4, 5, 7, 8  
10, 11, 13, 42  
44, 45, 47, 48  
50, 51, 53  
DQ0- DQ15 Input/ Data I/O: Data bus.  
Output  
36, 40  
NC  
No Connect: These pins should be left unconnected.  
3, 9, 43, 49  
6, 12, 46, 52  
1, 14, 27  
VDDQ  
VSSQ  
VDD  
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.  
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.  
Supply Power Supply: +3.3V ±0.3V.  
28, 41, 54  
VSS  
Supply Ground.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD4M16  
Rev. 1.5 10/01  
5
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