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AS4SD4M16DG-10/XT 参数 Datasheet PDF下载

AS4SD4M16DG-10/XT图片预览
型号: AS4SD4M16DG-10/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 4梅格×16 SDRAM同步动态随机存取存储 [4 Meg x 16 SDRAM Synchronous DRAM Memory]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 50 页 / 1139 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SDRAM  
AS4SD4M16  
Austin Semiconductor, Inc.  
Table 1  
BURST DEFINITION  
BURST TYPE  
Accesses within a given burst may be programmed to  
Burst  
Length  
Starting Column  
Order of Access Within a Burst  
be either sequential or interleaved; this is referred to as the  
burst type and is selected via bit M3.  
The ordering of accesses within a burst is determined  
by the burst length, the burst type and the starting column  
address, as shown in Table 1.  
Address  
Type = Sequential Type = Interleaved  
A0  
0
1
2
4
0 - 1  
1-0  
0 - 1  
1-0  
A1  
0
0
1
1
A0  
0
1
0
1
0,1,2,3  
1,2,3,0  
2,3,0,1  
3,0,1,2  
0,1,2,3  
1,0,3,2  
2,3,0,1  
3,2,1,0  
A2  
0
0
0
0
1
1
1
1
A1  
0
0
1
1
0
0
1
1
A0  
0
1
0
1
0
1
0
1
0,1,2,3,4,5,6,7  
1,2,3,4,5,6,7,0  
2,3,4,5,6,7,0,1  
3,4,5,6,7,0,1,2  
4,5,6,7,0,1,2,3  
5,6,7,0,1,2,3,4  
6,7,0,1,2,3,4,5,  
7,0,1,2,3,4,5,6  
Cn, Cn+1, Cn+2,  
Cn+3, Cn+4…  
…Cn-1,  
0,1,2,3,4,5,6,7  
1,0,3,2,5,4,7,6  
2,3,0,1,6,7,4,5  
3,2,1,0,7,6,5,4  
4,5,6,7,0,1,2,3  
5,4,7,6,1,0,3,2  
6,7,4,5,2,3,0,1  
7,6,5,4,3,2,1,0  
8
Not Supported  
Full Page  
(y)  
n = A0 - A9  
location 0 - y  
Cn…  
A11  
11  
A10  
10  
A9  
A8  
8
A7  
7
A6  
6
A5  
A4  
4
A3  
A2  
2
A1  
A0 Address Bus  
Mode Register(Mx)  
9
5
3
1
0
Reserved*  
WB  
Op Mode  
CAS Latency  
BT  
Burst Length  
Burst Length  
M3=0  
1
2
M3=1  
1
2
M2  
0
0
M1  
0
0
M0  
0
1
* Should program M11,  
M10=0,0 to ensure  
compatibility with future  
devices.  
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
4
8
4
8
NOTE:  
Reserved  
Reserved  
Reserved  
Full Page  
Reserved  
Reserved  
Reserved  
Reserved  
1. For full-page accesses: y = 256 (x16).  
2. For a burst length of two, A1-A7 (x16)  
select the block-of-two burst; A0 selects  
the starting column within the block.  
3. For a burst length of four, A2-A7 (x16)  
select the block-of-four burst; A0-A1  
select the starting column within the  
block.  
M3  
0
1
Burst Type  
Sequential  
Interleave  
M6  
0
0
M5  
0
0
M4  
0
1
CAS Latency  
Reserved  
Reserved  
2
0
1
0
4. For a burst length of eight, A3-A7 (x16)  
select the clock-of-eight burst; A0-A2  
select the starting column within the  
block.  
0
1
1
1
1
0
0
1
1
0
1
0
3
Reserved  
Reserved  
Reserved  
Reserved  
1
1
1
M8  
0
-
M7  
0
-
5. For a full-page burst, the full row is  
selected and A0-A7 (x16) select the  
starting column.  
M6 - M0  
Defined  
-
Operating Mode  
Standard Operation  
All other states reserved  
6. Whenever a boundary of the block is  
reached within a given sequence above,  
the following access wraps within the  
block.  
M9  
0
1
Write Burst Mode  
Programmed Burst Length  
Single Location Access  
7. For a burst length of one, A0-A7 (x16)  
select the unique column to be accessed,  
and Mode Register bit M3 is ignored.  
FIGURE 1  
MODE REGISTER DEFINITION  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD4M16  
Rev. 1.5 10/01  
7
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