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AS4SD4M16DG-10/XT 参数 Datasheet PDF下载

AS4SD4M16DG-10/XT图片预览
型号: AS4SD4M16DG-10/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 4梅格×16 SDRAM同步动态随机存取存储 [4 Meg x 16 SDRAM Synchronous DRAM Memory]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 50 页 / 1139 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SDRAM  
AS4SD4M16  
Austin Semiconductor, Inc.  
CAS Latency  
Reserved states should not be used as unknown op-  
The CAS latency is the delay, in clock cycles, between eration or incompatibility with future versions may result.  
the registration of a READ command and the availability of the Operating Mode  
first piece of output data. The latency can be set to two or three  
clocks.  
The normal operating mode is selected by setting  
M7and M8 to zero; the other combinations of values for M7  
If a READ command is registered at clock edge n, and and M8 are reserved for future use and/or test modes. The  
the latency is m clocks, the data will be available by clock edge programmed burst length applies to both READ and WRITE  
n+m. The DQs will start driving as a result of the clock edge one bursts.  
cycle earlier (n + m - 1), and provided that the relevant access  
Test modes and reserved states should not be used  
times are met, the data will be valid by clock edge n + m. For because unknown operation or incompatibility with future ver-  
example, assuming that the clock cycle time is such that all sions may result.  
relevant access times are met, if a READ command is registered Write Burst Mode  
at T0 and the latency is programmed to two clocks, the DQs will  
When M9 = 0, the burst length programmed via M0-  
start driving after T1 and the data will be valid by T2, as shown M2 applies to both READ and WRITE bursts; when M9 = 1,  
in Figure 2. Table 2 below indicates the operating frequencies at the programmed burst length applies to READ bursts, but write  
which each CAS latency setting can be used.  
accesses are single-location (nonburst) accesses.  
Table 2  
CAS LATENCY  
T0  
T1  
T2  
T3  
CLK  
ALLOWABLE OPERATING FREQUENCY  
(MHz)  
READ  
NOP  
NOP  
COMMAMD  
DQ  
CAS LATENCY = 2  
CAS LATENCY = 3  
125  
SPEED  
-8  
-10  
tLZ  
tOH  
DOUT  
≤ 83  
≤ 66  
100  
tAC  
CAS Latency = 2  
T0  
T1  
T2  
T3  
T4  
CLK  
NOP  
READ  
NOP  
tLZ  
NOP  
tOH  
COMMAMD  
DQ  
DOUT  
tAC  
CAS Latency = 3  
UNDEFINED  
DON’T CARE  
Figure 2  
CAS LATENCY  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD4M16  
Rev. 1.5 10/01  
8
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