SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
4
Interrupted by a WRITE (with or without AUTO
WRITE with AUTO PRECHARGE
PRECHARGE): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRECHARGE to
3. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a
WRITE on bank n when registered, with the data-out
appearing CAS latency later. The PRECHARGE to bank
bank n will begin after tWR is met, where tWR begins when
the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior
to a WRITE to bank 1 (Figure 27).
will begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
T7
T0
T1
T2
T3
T4
T5
T6
CLK
WRITE-AP
BANKm
WRITE-AP
BANK n
COMMAND
NOP
NOP
NOP
NOP
NOP
Precharge
NOP
BANK n
Internal
States
WRITE with burst of 4
Interrupt Burst, Write back
Page Active
tRP-BANK m
tRP-BANK n
tWR - BANK n
Page Active
BANK m
READ with burst of 4
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
a+1
IN
DIN
a
DOUT d+1
DOUT
d
CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 26
WRITE WITH AUTO PRECHARGE INTERRUPTED BY A READ
T7
T6
T0
T1
T2
T3
T4
T5
CLK
WRITE-AP
BANKm
WRITE-AP
BANK n
NOP
COMMAND
NOP
NOP
NOP
NOP
Precharge
NOP
BANK n
Internal
States
Page Active
Interrupt Burst, Write back
WRITE with burst of 4
tWR-BANK m
tRP-BANK n
t
- BANK n
WR
Page Active
BANK m
WRITE with burst of 4
Write back
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
a+1
D
D
D
D
IN
D
a+2
IN
IN
dIN
d+1
d+2
IN
IN
DIN
a
d+3
Don’t Care
NOTE: DQM is LOW.
Figure 27
WRITE WITH AUTO PRECHARGE INTERRUPTED BY A WRITE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
24
AUSTIN [ AUSTIN SEMICONDUCTOR ]
