SDRAM
AS4SD2M32
Austin Semiconductor, Inc.
TRUTH TABLE 3: CURRENT STATE BANK n, COMMAND TO BANK n1,2,3,4,5,6
CURRENT STATE CS\ RAS\ CAS\ WE\
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and active row)
AUTO REFRESH
LOAD MODE REGISTER
NOTES
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
X
H
H
L
L
H
L
L
H
L
X
H
H
H
L
L
H
L
L
H
L
L
L
ANY
7
7
11
10
10
8
10
10
8
Idle
L
PRECHARGE
H
H
L
H
H
L
H
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Row Active
Read
(Auto Precharge
Disabled)
L
H
H
L
L
H
H
9
H
L
L
10
10
8
Write
(Auto Precharge
Disabled)
H
L
9
NOTES:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous
state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read:
Write:
A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been
terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been
terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands,
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.
Precharging:
Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the
bank will be in the idle state.
Row Activating:
Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the
bank will be in the row active state.
Read w/ Auto
Precharge Enabled:
Starts with registration of a READ command with auto precharge enabled and ends when tRP has
been met. Once tRP is met, the bank will be in the idle state.
Write w/ Auto
Precharge Enabled:
Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has
been met. Once tRP is met, the bank will be in the idle state.
(continued on next page)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD2M32
Rev. 1.0 1/08
23
AUSTIN [ AUSTIN SEMICONDUCTOR ]
