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AS4SD2M32DGX-6XT 参数 Datasheet PDF下载

AS4SD2M32DGX-6XT图片预览
型号: AS4SD2M32DGX-6XT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32× 4银行( 64 MB) SDRAM同步 [512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM]
分类和应用: 内存集成电路光电二极管动态存储器
文件页数/大小: 52 页 / 1943 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SDRAM  
AS4SD2M32  
Austin Semiconductor, Inc.  
NOTES (continued):  
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state  
only.  
6. All states and sequences not shown are illegal or reserved.  
7. READs or WRITEs to bank m listed in the Command column include READs or WRITEs with auto precharge enabled and  
READs or WRITEs with auto precharge disabled.  
8. CONCURRENT AUTO PRECHARGE: bank n will initiate the auto precharge command when its burst has been interrupted by  
bank m’s burst.  
9. Burst in bank n continues as initiated.  
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt  
the READ on bank n, CAS latency later (Figure 7).  
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will  
interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command  
to prevent bus contention.  
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will  
interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE  
to bank n will be data-in registered one clock prior to the READ on bank m.  
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will  
interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock  
prior to the READ to bank m.  
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt  
the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure  
25).  
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt  
the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention.  
The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).  
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt  
the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after  
t
WR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered  
one clock prior to the READ to bank m (Figure 26).  
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt  
the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE  
to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD2M32  
Rev. 1.0 1/08  
26  
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