SDRAM
AS4SD2M32
Austin Semiconductor, Inc.
CLOCKSUSPEND
Clock suspend more is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
The clock suspend mode occurs when a column access/
burst is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing” the
synchronous logic.
BURSTREAD/SINGLEWRITE
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended. Any
command or data present on the input pins at the time of a
suspected internal clock edge is ignored; any data present on
the DQ pins remains driven; and burst counters are not
incremented, as long as the clock is suspended. (See examples
in Figure 22 and 23).
The burst read/single write mode is entered by
programming the write burst mode bit (M9) in the mode register
to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
FIGURE 22: Clock Suspend During WRITE Burst
FIGURE 23: Clock Suspend During READ Burst
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD2M32
Rev. 1.0 1/08
19
AUSTIN [ AUSTIN SEMICONDUCTOR ]
