AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
RAS-ONLY REFRESH CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
t
RPC
CRP
V
V
IH
IL
CASL/CASH
t
t
RAH
ASR
V
V
IH
IL
ADDR
ROW
ROW
V
V
OH
OL
Q
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE
NOTE 1
CBR REFRESH CYCLE
(Addresses and OE = DON’T CARE)
t
t
t
t
RAS
RP
RAS
RP
V
V
IH
IL
RAS
t
RPC
t
t
t
t
t
t
CHR
RPC
CP
CSR
CHR
CSR
V
V
IH
IL
CASL and CASH
DQ
V
V
OH
OL
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE
NOTE 2
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should
implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
t
2. WRP and tWRH are for system design reference only. The WE signal is actually a “don’t care” at RAS time during a CBR
REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to ensure compatibility with other
DRAMs that require WE HIGH at RAS time during a CBR REFRESH.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
MAX
MIN
0
MAX
MIN
0
MAX
UNITS
ns
SYM MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ns
tASR
tCHR
tCP
tCRP
tCSR
tRAH
0
10
10
5
tRAS
tRC
tRP
tRPC
tWRH
tWRP
60 10,000
70 10,000 80 10,000
12
10
5
15
10
5
ns
105
40
5
125
50
5
150
60
5
ns
ns
ns
ns
ns
5
5
10
10
ns
10
10
10
10
10
10
ns
10
10
ns
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-111
AUSTIN [ AUSTIN SEMICONDUCTOR ]
