AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t
t
RP
RASP
V
V
IH
IL
RAS
t
CSH
t
t
t
PC
RSH
PC
t
t
t
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS, CLCH
CP
CAS, CLCH
CP
CAS, CLCH
V
V
IH
IL
CASL/CASH
t
t
t
RAL
AR
t
t
t
RAD
ACH
CAH
t
ASR
t
t
t
t
t
ASC
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE
ROW
t
COLUMN (A)
COLUMN (B)
ROW
COLUMN (N)
t
t
t
RCH
t
t
WRP
WRH
t
RCS
WCS
WCH
V
V
IH
IL
t
AA
t
t
NOTE 1
AA
t
CPA
RAC
t
t
DH
t
CAC
DS
CAC
t
t
WHZ
VALID
COH
V
V
IOH
IOL
DQ
OE
OPEN
VALID DOUT
VALID DIN
DOUT
t
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
SYM MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ns
30
35
40
tPC
25
30
40
15
45
0
15
50
0
20
60
0
ns
tRAC
tRAD
tRAH
tRAL
60
30
70
35
80
40
ns
tAR
ns
12
10
30
12
10
35
15
10
40
ns
tASC
tASR
tCAC
tCAH
tCAS
ns
ns
0
0
0
ns
ns
15
20
20
ns
tRASP 60
125,000
45
70 125,000
80 100,000
ns
10
12
15
ns
tRCD
tRCH
tRCS
tRP
tRSH
tWCH
tWCS
tWHZ
tWRH
tWRP
14
0
14
0
50
15
20
0
60
20
ns
12 10,000
13 10,000
20 10,000
ns
ns
tCLCH 10
10
3
10
5
ns
0
0
0
ns
tCOH
tCP
3
ns
40
13
10
0
50
15
12
0
60
15
15
0
ns
10
10
40
5
10
40
5
ns
ns
tCPA
tCRP
tCSH
tDH
35
15
ns
ns
5
50
10
0
ns
ns
55
12
0
60
15
0
ns
0
13
0
0
ns
ns
10
10
10
10
10
10
ns
tDS
ns
ns
tOE
20
20
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-109
AUSTIN [ AUSTIN SEMICONDUCTOR ]
