AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
READ CYCLE
(with WE-controlled disable)
V
IH
RAS
CASL/CASH
ADDR
V
IL
t
CSH
t
t
t
t
t
t
RCD
CAS, CLCH
CRP
CP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
ASR
ASC
CAH
ASC
V
V
IH
IL
ROW
t
COLUMN
COLUMN
t
t
WRP
WRH
RCS
t
t
t
RCH
WPZ
RCS
V
V
WE
IH
IL
NOTE 1
t
t
t
t
AA
RAC
CAC
CLZ
t
t
WHZ
CLZ
V
V
OH
OL
DQ
OE
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
MAX
MIN
MAX
MIN
MAX
UNITS
ns
SYM MIN
MAX
15
MIN
MAX
15
MIN
MAX
15
UNITS
ns
30
35
40
tOD
0
0
0
tAR
45
0
50
0
60
0
ns
tOE
15
20
20
ns
tASC
tASR
tCAC
tCAH
tCAS
ns
tRAC
tRAD
tRAH
tRCD
tRCH
tRCS
tWHZ
tWPZ
tWRH
tWRP
60
70
80
ns
0
0
0
ns
12
10
14
0
30
12
10
14
0
35
15
10
20
0
40
ns
15
20
20
ns
ns
10
12
15
ns
45
13
50
15
60
20
ns
12 10,000
13 10,000
20 10,000
ns
ns
tCLCH 10
10
0
10
0
ns
0
0
0
ns
tCLZ
tCP
tCRP
tCSH
0
10
5
ns
0
0
0
ns
10
5
10
5
ns
10
10
10
12
10
10
15
10
10
ns
ns
ns
50
55
60
ns
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-110
AUSTIN [ AUSTIN SEMICONDUCTOR ]
