AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE READ CYCLE
t
t
RASP
RP
V
V
IH
IL
RAS
t
t
t
t
RSH
CSH
PC
CP
t
t
t
t
t
t
t
t
t
t
CP
CAS, CLCH
CAS, CLCH
CAS, CLCH
CRP
RCD
CP
V
V
CASL/CASH
IH
IL
t
AR
t
t
t
ACH
ACH
ACH
t
t
t
RAD
RAH
RAL
t
t
t
t
t
t
t
t
ASR
ASC
RCS
CAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
WRH
WRP
t
RCH
V
V
IH
IL
t
t
t
t
RRH
AA
NOTE 1
t
t
t
t
AA
AA
CPA
CAC
t
RAC
CPA
CAC
t
t
CAC
CLZ
t
OEHC
t
OFF
t
COH
t
CLZ
V
OH
OL
VALID
DATA
VALID
DATA
VALID
DATA
DQ
OE
OPEN
OPEN
V
t
t
t
OE
OE
t
OD
OD
t
OES
t
V
V
OES
IH
IL
t
OEP
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM MIN
MAX
MIN
10
5
MAX
MIN
10
5
MAX
UNITS
ns
ns
30
35
40
tOEP
tOES
tOFF
tPC
10
5
15
45
0
15
50
0
20
60
0
tAR
3
15
3
15
0
20
ns
tASC
tASR
tCAC
tCAH
tCAS
30
35
40
ns
0
0
0
tRAC
tRAD
tRAH
tRAL
60
30
70
35
80
40
ns
ns
ns
ns
15
20
20
12
10
30
12
10
35
15
10
40
10
12
12
15
10,000 13 10,000 20 10,000
tCLCH 10
10
0
10
0
tRASP 60
100,000 70 100,000 80 100,000
ns
tCLZ
tCOH
tCP
0
3
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
14
0
45
14
0
50
20
0
60
ns
3
5
ns
10
10
10
0
0
0
ns
tCPA
tCRP
tCSH
tOD
35
40
40
40
0
50
0
60
0
ns
5
50
0
5
55
0
5
60
0
ns
13
10
10
15
10
10
15
10
10
ns
ns
15
15
15
20
20
20
tOE
tOEHC 10
ns
10
10
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-106
AUSTIN [ AUSTIN SEMICONDUCTOR ]
