AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
t
RP
RASP
V
V
IH
IL
RAS
t
t
t
t
CSH
PC
CP
RSH
t
t
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS, CLCH
CAS, CLCH
CP
CAS, CLCH
V
V
IH
IL
CASL/CASH
t
t
AR
ACH
t
t
t
t
t
RAD
ACH
RAL
ACH
ASC
t
t
t
t
t
t
t
ASC
ASR
RAH
CAH
ASC
CAH
CAH
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
t
t
t
t
t
CWL
CWL
WCH
WP
CWL
WCH
WP
t
t
t
t
t
WCS
WCS
WCH
WP
WCS
t
t
WRH
WRP
V
V
IH
IL
WE
NOTE 1
t
t
t
t
WCR
DHR
DH
RWL
t
t
t
t
t
DS
DS
DH
DS
DH
V
IOH
IOL
DQ
OE
VALID DATA
VALID DATA
VALID DATA
V
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
MAX
MIN
15
50
0
MAX
MIN
20
60
0
MAX
UNITS
ns
SYM MIN
MAX
MIN
12
MAX
MIN
15
MAX
UNITS
ns
tACH
tAR
tASC
tASR
tCAH
tCAS
15
45
0
tRAD
tRAH
tRAL
12
10
30
30
35
40
ns
10
10
ns
ns
35
40
ns
0
0
0
ns
tRASP 60 125,000 70 125,000 80 100,000
ns
10
12
15
ns
tRCD
tRP
14
40
13
15
10
45
0
45
14
50
15
15
12
55
0
50
20
60
15
20
15
60
0
60
ns
12 10,000
13 10,000 20 10,000
ns
ns
tCLCH 10
10
10
5
10
10
5
ns
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
ns
tCP
10
5
ns
ns
tCRP
tCSH
tCWL
tDH
tDHR
tDS
ns
ns
50
15
10
45
0
55
15
12
55
0
60
20
15
55
0
ns
ns
ns
ns
ns
10
10
10
12
10
10
15
10
10
ns
ns
tWRH
tWRP
ns
ns
ns
tPC
25
30
40
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-107
AUSTIN [ AUSTIN SEMICONDUCTOR ]
