AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
t
RP
RASP
V
V
IH
IL
RAS
t
t
t
NOTE 1
t
CSH
PC
PRWC
t
RSH
t
t
t
t
t
t
CP
t
t
t
t
CRP
RCD
CP
CP
CAS, CLCH
CAS, CLCH
CAS, CLCH
CASL/CASH
V
V
IH
IL
t
AR
t
t
t
RAD
RAH
RAL
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
CWL
t
RCS
t
t
CWL
CWL
t
t
t
WP
WP
WP
t
t
t
t
t
AWD
AWD
AWD
CWD
t
t
WRH
t
WRP
CWD
CWD
WE
V
V
IH
IL
NOTE 2
t
t
t
AA
AA
AA
t
RAC
t
t
t
DH
DH
DH
t
t
CPA
CPA
t
t
t
DS
DS
DS
t
t
t
t
t
t
CAC
CLZ
CAC
CLZ
CAC
CLZ
V
IOH
IOL
VALID VALID
VALID VALID
VALID VALID
D D
DQ
OE
OPEN
OPEN
V
D
D
D
D
OUT
IN
OUT
IN
OUT
IN
t
t
t
OD
OD
OD
t
OEH
t
t
t
OE
OE
OE
V
V
IH
IL
DON’T CARE
UNDEFINED
t
NOTE:
1. PC is for LATE WRITE cycles only.
2. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM MIN
tOE
tOEH
tPC
tPRWC 75
tRAC
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
35
40
15
20
20
tAR
45
0
50
0
60
0
12
25
12
30
85
15
40
90
tASC
tASR
tAWD
tCAC
tCAH
tCAS
0
0
0
55
60
65
60
30
70
35
80
40
15
20
20
tRAD
tRAH
tRAL
12
10
30
12
10
35
15
10
40
10
12
15
12 10,000
13 10,000
20 10,000
tCLCH 10
10
0
10
0
tRASP 60
125,000
45
70 125,000
80 100,000
tCLZ
tCP
0
tRCD
tRCS
tRP
tRSH
tRWD
tRWL
tWP
14
0
14
0
50
20
0
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
40
5
10
40
5
tCPA
tCRP
tCSH
tCWD
tCWL
tDH
35
15
40
13
80
15
10
10
10
50
15
90
15
12
10
10
60
15
105
20
15
10
10
5
50
35
15
10
0
55
40
15
12
0
60
45
20
15
0
tWRH
tWRP
tDS
tOD
0
0
15
0
20
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-108