AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
READ CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
t
RRH
RSH
t
t
t
CLCH
t
RCD
CAS
CRP
V
V
IH
IL
CASL/CASH
t
AR
t
t
t
t
t
RAD
RAH
RAL
CAH
ACH
t
t
ASC
ASR
V
V
IH
IL
ROW
t
ROW
ADDR
COLUMN
t
t
t
RCH
WRP
WRH
RCS
V
V
WE
IH
IL
NOTE 1
t
t
t
t
AA
NOTE 2
OFF
RAC
CAC
CLZ
t
V
V
OH
OL
DQ
OE
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
2. OFF is referenced from rising edge of RAS or CAS, whichever occurs last.
t
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
SYM MIN
tRAC
MAX
60
MIN
MAX
70
MIN
MAX
80
UNITS
ns
30
35
40
15
45
0
15
50
0
20
60
0
ns
tRAD
tRAH
tRAL
tRAS
tRC
12
10
30
30
12
10
35
35
15
10
40
40
ns
tAR
ns
ns
tASC
tASR
tCAC
tCAH
tCAS
ns
ns
0
0
0
ns
60 10,000
110
70 10,000 80 10,000
ns
15
20
20
ns
130
14
0
150
20
0
ns
10
12
15
ns
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
14
0
45
50
60
ns
12 10,000
13 10,000 20 10,000
ns
ns
tCLCH 10
10
0
10
0
ns
0
0
0
ns
tCLZ
tCRP
tCSH
tOD
0
5
ns
40
0
50
0
60
0
ns
5
5
ns
ns
50
0
55
0
60
0
ns
13
10
10
15
10
10
15
10
10
ns
15
15
15
15
20
15
20
20
20
ns
ns
tOE
ns
ns
tOFF
0
0
0
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-103
AUSTIN [ AUSTIN SEMICONDUCTOR ]
