AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
NOTES
1. All voltages referenced to VSS.
17. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, WE
must be pulsed during CAS HIGH time in order to
place I/ O buffers in High-Z.
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C ≤ TA ≤ 70˚C) is assured.
3. An initial pause of 100µs is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
18. LATE WRITE and READ-MODIFY-WRITE cycles
t
t
must have both OD and OEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously read data if CAS
t
repeated any time the REF refresh requirement is
exceeded.
t
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VCC = +3.0V; f = 1 MHz.
remains LOW and OE is taken back LOW after OEH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
t
t
t
19. Assumes that RCD < RCD (MAX). If RCD is greater
than the maximum recommended value shown in this
t
t
table, RAC will increase by the amount that RCD
exceeds the value shown.
20. OFF (MAX) defines the time at which the output
t
t
9. AC characteristics assume T = 2.5ns.
achieves the open circuit condition, and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS or CAS, whichever occurs last.
10. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
t
21. Operation within the RAD (MAX) limit ensures that
t
t
t
RAC (MIN) and CAC (MIN) can be met. RAD
t
11. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
12. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
(MAX) is specified as a reference point only; if RAD
is greater than the specified RAD (MAX) limit, then
t
t
access time is controlled exclusively by AA, provided
t
RCD is not exceeded.
t
22. Operation within the RCD (MAX) limit ensures that
t
t
t
t
t
t
13. WCS, RWD, AWD and CWD are not restrictive
RAC (MAX) can be met. RCD (MAX) is specified as
t
t
operating parameters. WCS applies to EARLY
WRITE cycles. RWD, AWD and CWD apply to
READ-MODIFY-WRITE cycles. If WCS ≥ WCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
a reference point only; if RCD is greater than the
specified RCD (MAX) limit, then access time is
controlled exclusively by CAC, provided RAD is not
exceeded.
t
t
t
t
t
t
t
t
t
t
23. Either RCH or RRH must be satisfied for a READ
cycle.
t
t
t
the entire cycle. If WCS < WCS (MIN) and RWD ≥
t
t
t
t
t
RWD (MIN), AWD ≥ AWD (MIN) and CWD ≥
CWD (MIN), the cycle is a READ-MODIFY-WRITE
24. The first CASx edge to transition LOW.
25. Output parameter (DQx) is referenced to correspond-
ing CAS input; DQ1-DQ8 by CASL and DQ9-DQ16
by CASH.
26. Each CASx must meet minimum pulse width.
27. The last CASx edge to transition HIGH.
28. Last falling CASx edge to first rising CASx edge.
29. Last rising CASx edge to first falling CASx edge.
30. Last rising CASx edge to next cycle’s last rising CASx
edge.
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE held HIGH
and WE taken LOW after CAS goes LOW results in a
t
t
LATE WRITE (OE-controlled) cycle. WCS, RWD,
t
t
CWD and AWD are not applicable in a LATE
WRITE cycle.
t
t
14. Assumes that RCD ≥ RCD (MAX).
15. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
31. Last CASx to go LOW.
32. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE = HIGH.
t
pulsed HIGH for CP.
16. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-102
AUSTIN [ AUSTIN SEMICONDUCTOR ]
