Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)
T1
T2
T3
T4
T5
T6
System Clock (CLKCPU
)
ALE
A15:8 Prev. addr.
DA7:0 Prev. data
WR
Address
Data
Address
Address
XX
DA7:0 (XMBK = 0) Prev. data
DA7:0 (XMBK = 1) Prev. data
RD
Data
Data
Address
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T6 is only present if the next instruction accesses the RAM
(internal or external).
Figure 17. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)
T1
T2
T3
T4
T5
T6
T7
System Clock (CLKCPU
)
ALE
A15:8 Prev. addr.
DA7:0 Prev. data
WR
Address
Data
Address
Address
XX
DA7:0 (XMBK = 0) Prev. data
DA7:0 (XMBK = 1) Prev. data
RD
Data
Data
Address
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM
(internal or external).
XMEM Register Description
External Memory Control
Register A – XMCRA
Bit
7
6
SRL2
R/W
0
5
SRL1
R/W
0
4
SRL0
R/W
0
3
SRW11
R/W
0
2
SRW10
R/W
0
1
SRW01
R/W
0
0
SRW00
R/W
0
SRE
R/W
0
XMCRA
Read/Write
Initial Value
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-
28
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
