Note:
1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see
Figures 14 through Figures 17 for how the setting of the SRW bits affects the timing.
External Memory Control
Register B – XMCRB
Bit
7
XMBK
R/W
0
6
–
5
–
4
–
3
–
2
XMM2
R/W
0
1
XMM1
R/W
0
0
XMM0
R/W
0
XMCRB
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper
is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would
otherwise be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not
qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still
activated as long as XMBK is one.
• Bit 6..4 – Reserved Bits
These are reserved bits and will always read as zero. When writing to this address loca-
tion, write these bits to zero for compatibility with future devices.
• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high
address byte. If the full 60KB address space is not required to access the External Mem-
ory, some, or all, Port C pins can be released for normal Port Pin function as described
in Table 4. As described in “Using all 64KB Locations of External Memory” on page 31,
it is possible to use the XMMn bits to access all 64KB locations of the External Memory.
Table 4. Port C Pins Released as Normal Port Pins when the External Memory is
Enabled
XMM2 XMM1 XMM0 # Bits for External Memory Address
Released Port Pins
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 (Full 60 KB space)
7
PC7
6
PC7 .. PC6
PC7 .. PC5
PC7 .. PC4
PC7 .. PC3
PC7 .. PC2
Full Port C
5
4
3
2
No Address high bits
30
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
