Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The External Memory Interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
•
•
•
D to Q propagation delay (tPD).
Data setup time before G low (tSU).
Data (address) hold time after G low (TH).
The External Memory Interface is designed to guaranty minimum address hold time
after G is asserted low of th = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in “Memory Programming”
Tables 142 through Tables 149. The D-to-Q propagation delay (tPD) must be taken into
consideration when calculating the access time requirement of the external component.
The data setup time before G low (tSU) must not exceed address valid to ALE low (tAV-
LLC) minus PCB wiring delay (dependent on the capacitive load).
Figure 13. External SRAM Connected to the AVR
D[7:0]
AD7:0
ALE
D
G
Q
A[7:0]
SRAM
A[15:8]
AVR
A15:8
RD
RD
WR
WR
Pull-up and Bus-keeper
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is
written to one. To reduce power consumption in sleep mode, it is recommended to dis-
able the pull-ups by writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper
can be disabled and enabled in software as described in “External Memory Control Reg-
ister B – XMCRB” on page 30. When enabled, the bus-keeper will ensure a defined logic
level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated by
the XMEM interface.
Timing
External Memory devices have different timing requirements. To meet these require-
ments, the AT90CAN128 XMEM interface provides four different wait-states as shown
in Table 3. It is important to consider the timing specification of the External Memory
device before selecting the wait-state. The most important parameters are the access
time for the external memory compared to the set-up requirement of the AT90CAN128.
The access time for the External Memory is defined to be the time from receiving the
chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data
is stable during a read sequence (See tLLRL+ tRLRH - tDVRH in Tables 142 through Tables
149). The different wait-states are set up in software. As an additional feature, it is pos-
sible to divide the external memory space in two sectors with individual wait-state
26
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
