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MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
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AT90CAN128  
Figure 12. External Memory with Sector Select  
0x0000  
Internal memory  
0x10FF  
0x1100  
Lower sector  
SRW01  
SRW00  
SRL[2..0]  
External Memory  
(0-60K x 8)  
Upper sector  
SRW11  
SRW10  
0xFFFF  
Using the External Memory  
Interface  
The interface consists of:  
AD7:0: Multiplexed low-order address bus and data bus.  
A15:8: High-order address bus (configurable number of bits).  
ALE: Address latch enable.  
RD: Read strobe.  
WR: Write strobe.  
The control bits for the External Memory Interface are located in two registers, the Exter-  
nal Memory Control Register A – XMCRA, and the External Memory Control Register B  
– XMCRB.  
When the XMEM interface is enabled, the XMEM interface will override the setting in the  
data direction registers that corresponds to the ports dedicated to the XMEM interface.  
For details about the port override, see the alternate functions in section “I/O-Ports” on  
page 61. The XMEM interface will auto-detect whether an access is internal or external.  
If the access is external, the XMEM interface will output address, data, and the control  
signals on the ports according to Figure 14 (this figure shows the wave forms without  
wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is  
low during a data transfer. When the XMEM interface is enabled, also an internal access  
will cause activity on address, data and ALE ports, but the RD and WR strobes will not  
toggle during internal access. When the External Memory Interface is disabled, the nor-  
mal pin and data direction settings are used. Note that when the XMEM interface is  
disabled, the address space above the internal SRAM boundary is not mapped into the  
internal SRAM. Figure 13 illustrates how to connect an external SRAM to the AVR using  
an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.  
25  
4250E–CAN–12/04  
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