AT90CAN128
Timer/Counter3 Control
Register C – TCCR3C
Bit
7
FOC3A
R/W
0
6
FOC3B
R/W
0
5
FOC3C
R/W
0
4
–
3
–
2
–
1
–
0
–
TCCR3C
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a
non-PWM mode. However, for ensuring compatibility with future devices, these bits
must be set to zero when TCCRnA is written when operating in a PWM mode. When
writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is
forced on the Waveform Generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are
implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that
determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer
in Clear Timer on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnC bits are always read as zero.
Timer/Counter1 – TCNT1H and
TCNT1L
Bit
7
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1[7:0]
TCNT1H
TCNT1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
Timer/Counter3 – TCNT3H and
TCNT3L
Bit
7
6
5
4
3
2
1
0
TCNT3[15:8]
TCNT3[7:0]
TCNT3H
TCNT3L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 111
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing
a compare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following
timer clock for all compare units.
135
4250E–CAN–12/04
ATMEL [ ATMEL ]
