Table 61 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the
fast PWM mode.
Table 61. Compare Output Mode, Fast PWM(1)
COMnA1/COMnB1/ COMnA0/COMnB0/
COMnC1
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC
disconnected.
0
1
WGMn3=0: Normal port operation,
OCnA/OCnB/OCnC disconnected.
WGMn3=1: Toggle OCnA on Compare Match,
OCnB/OCnC reserved.
1
1
0
1
Clear OCnA/OCnB/OCnC on Compare Match
Set OCnA/OCnB/OCnC at TOP
Set OCnA/OCnB/OCnC on Compare Match
Clear OCnA/OCnB/OCnC at TOP
Note:
1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but
the set or clear is done at TOP. See “Fast PWM Mode” on page 122 for more details.
Table 62 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the
phase correct or the phase and frequency correct, PWM mode.
Table 62. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM(1)
COMnA1/COMnB1/ COMnA0/COMnB0/
COMnC1
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC
disconnected.
0
1
1
1
0
1
WGMn3=0: Normal port operation,
OCnA/OCnB/OCnC disconnected.
WGMn3=1: Toggle OCnA on Compare Match,
OCnB/OCnC reserved.
Clear OCnA/OCnB/OCnC on Compare Match
when up-counting.
Set OCnA/OCnB/OCnC on Compare Match when
downcounting.
Set OCnA/OCnB/OCnC on Compare Match when
up-counting.
Clear OCnA/OCnB/OCnC on Compare Match
when downcounting.
Note:
1. A special case occurs when OCnA/OCnB/OCnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. See “Phase Correct PWM Mode” on page 124
for more details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used, see Table 63. Modes of operation sup-
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare
132
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
