AT90CAN128
match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See
“Modes of Operation” on page 121 ).
Table 63. Waveform Generation Mode Bit Description(1)
WGMn2
(CTCn)
WGMn1
WGMn0
Timer/Counter Mode of
Update of
OCRnx at
TOVn Flag
Set on
Mode WGMn3
(PWMn1) (PWMn0) Operation
TOP
0
1
2
3
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Normal
0xFFFF Immediate
MAX
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
0x00FF
0x01FF
0x03FF
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
PWM, Phase Correct, 10-
bit
4
5
6
7
8
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
CTC
OCRnA
0x00FF
0x01FF
0x03FF
ICRn
Immediate
TOP
MAX
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
TOP
TOP
TOP
TOP
TOP
PWM, Phase and
Frequency Correct
BOTTOM
BOTTOM
9
1
0
0
1
PWM, Phase and
Frequency Correct
OCRnA
BOTTOM
BOTTOM
10
11
12
13
14
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
PWM, Phase Correct
PWM, Phase Correct
CTC
ICRn
OCRnA
ICRn
–
TOP
TOP
Immediate
–
BOTTOM
BOTTOM
MAX
(Reserved)
–
Fast PWM
ICRn
OCRnA
TOP
TOP
TOP
15
Fast PWM
TOP
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
Timer/Counter1 Control
Register B – TCCR1B
Bit
7
ICNC1
R/W
0
6
ICES1
R/W
0
5
–
4
WGM13
R/W
0
3
WGM12
R/W
0
2
CS12
R/W
0
1
CS11
R/W
0
0
CS10
R/W
0
TCCR1B
Read/Write
Initial Value
R
0
Timer/Counter3 Control
Register B – TCCR3B
Bit
7
ICNC3
R/W
0
6
ICES3
R/W
0
5
–
4
WGM33
R/W
0
3
WGM32
R/W
0
2
CS32
R/W
0
1
CS31
R/W
0
0
CS30
R/W
0
TCCR3B
Read/Write
Initial Value
R
0
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise can-
celer is activated, the input from the Input Capture pin (ICPn) is filtered. The filter
function requires four successive equal valued samples of the ICPn pin for changing its
output. The Input Capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
133
4250E–CAN–12/04
ATMEL [ ATMEL ]
