AT90CAN128
Initial Value
Bit
0
7
0
6
0
5
0
4
0
3
0
2
0
0
Input Capture Register –
ICR3H and ICR3L
1
0
ICR3[15:8]
ICR3[7:0]
ICR3H
ICR3L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs
on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 111
Timer/Counter1 Interrupt
Mask Register – TIMSK1
Bit
7
–
6
–
5
ICIE1
R/W
0
4
–
3
OCIE1C
R/W
0
2
OCIE1B
R/W
0
1
OCIE1A
R/W
0
0
TOIE1
R/W
0
TIMSK1
Read/Write
Initial Value
R
0
R
0
R
0
Timer/Counter3 Interrupt
Mask Register – TIMSK3
Bit
7
–
6
–
5
ICIE3
R/W
0
4
–
3
OCIE3C
R/W
0
2
OCIE3B
R/W
0
1
OCIE3A
R/W
0
0
TOIE3
R/W
0
TIMSK3
Read/Write
Initial Value
R
0
R
0
R
0
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIEn: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56 ) is executed when the ICFn
flag, located in TIFRn, is set.
• Bit 4 – Reserved Bit
This bit is reserved for future use.
• Bit 3 – OCIEnC: Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56 ) is executed when the
OCFnC flag, located in TIFRn, is set.
• Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56 ) is executed when the
OCFnB flag, located in TIFRn, is set.
137
4250E–CAN–12/04
ATMEL [ ATMEL ]
