ATmega64A
Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLPH
t XLXH
tPLXH
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 27-7 (i.e. tDVXH, tXHXL, and tXLDX) also apply to load-
ing operation.
Figure 27-9. Parallel Programming Timing, Reading Sequence (Within the Same Page) with
Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
BS1
tBHDV
tOLDV
OE
tOHDZ
ADDR1 (Low Byte)
DATA (High Byte)
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 27-7 (i.e. tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.
308
8160C–AVR–07/09
ATMEL [ ATMEL ]
