ATmega64A
Figure 27-1. Parallel Programming
+5V
+5V
RDY/BSY
OE
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC
WR
AVCC
PB7 - PB0
DATA
BS1
XA0
XA1
PAGEL
+12 V
BS2
RESET
PA0
XTAL1
GND
Table 27-6. Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
I/O Function
RDY/BSY
PD1
O
0: Device is busy programming, 1: Device is ready for
new command
OE
PD2
PD3
PD4
I
I
I
Output Enable (Active low)
Write Pulse (Active low)
WR
BS1
Byte Select 1 (“0” selects low byte, “1” selects high
byte)
XA0
PD5
PD6
PD7
PA0
I
I
I
I
XTAL Action Bit 0
XA1
XTAL Action Bit 1
PAGEL
BS2
Program Memory and EEPROM data Page Load
Byte Select 2 (“0” selects low byte, “1” selects 2’nd high
byte)
DATA
PB7 - 0
I/O Bi-directional Data bus (Output when OE is low)
Table 27-7. Pin Values Used to Enter Programming Mode
Pin
PAGEL
XA1
Symbol
Value
Prog_enable[3]
Prog_enable[2]
Prog_enable[1]
Prog_enable[0]
0
0
0
0
XA0
BS1
299
8160C–AVR–07/09
ATMEL [ ATMEL ]
