ATmega64A
27. Memory Programming
27.1 Program and Data Memory Lock Bits
The ATmega64A provides six Lock bits which can be left unprogrammed (“1”) or can be pro-
grammed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be
erased to “1” with the Chip Erase command.
Table 27-1. Lock Bit Byte(1)
Lock Bit Byte
Bit no
Description
–
Default Value
7
6
5
4
3
2
1
0
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
–
BLB12
BLB11
BLB02
BLB01
LB2
Boot Lock bit
Boot Lock bit
Boot Lock bit
Boot Lock bit
Lock bit
LB1
Lock bit
Note:
Table 27-2. Lock Bit Protection Modes(2)
Memory Lock Bits Protection Type
1. “1” means unprogrammed, “0” means programmed
LB Mode
LB2
1
LB1
1
1
2
No memory lock features enabled.
1
0
Further programming of the Flash and EEPROM is disabled in
Parallel and SPI/JTAG Serial Programming mode. The Fuse bits
are locked in both Serial and Parallel Programming mode.(1)
3
0
0
Further programming and verification of the Flash and
EEPROM is disabled in Parallel and SPI/JTAG Serial
Programming mode. The Fuse bits are locked in both Serial and
Parallel Programming mode.(1)
BLB0 Mode
BLB02
BLB01
1
1
1
No restrictions for SPM or LPM accessing the Application
section.
2
3
1
0
0
0
SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and LPM
executing from the Boot Loader section is not allowed to read
from the Application section. If Interrupt Vectors are placed in
the Boot Loader section, interrupts are disabled while executing
from the Application section.
4
0
1
LPM executing from the Boot Loader section is not allowed to
read from the Application section. If Interrupt Vectors are placed
in the Boot Loader section, interrupts are disabled while
executing from the Application section.
BLB1 Mode
BLB12
BLB11
295
8160C–AVR–07/09
ATMEL [ ATMEL ]
