ATmega64A
16.1 Register Description
16.1.1
SFIOR – Special Function IO Register
Bit
7
6
–
5
–
4
–
3
ACME
R/W
0
2
1
0
PSR321
R/W
0
0x20 (0x40)
Read/Write
Initial Value
TSM
R/W
0
PUD
R/W
0
PSR0
R/W
0
SFIOR
R
0
R
0
R
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to PSR0 and PSR321 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit written zero, the PSR0 and PSR321 bits are cleared by hardware, and
the Timer/Counters start counting simultaneously.
• Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
When this bit is one, the Timer/Counter3, Timer/Counter2, and Timer/Counter1 prescaler will be
reset. The bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that
Timer/Counter3 Timer/Counter2, and Timer/Counter1 share the same prescaler and a reset of
this prescaler will affect all three timers.
145
8160C–AVR–07/09
ATMEL [ ATMEL ]
