ATmega64A
Figure 17-3. Output Compare Unit, Block Diagram
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top
bottom
Waveform Generator
OCn
FOCn
WGMn1:0
COMn1:0
The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-
ering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled
the CPU will access the OCR2 directly.
17.5.1
17.5.2
17.5.3
Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the
OCF2 flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match
had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).
Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any Compare Match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized
to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all Compare Matches for one timer
clock cycle, there are risks involved when changing TCNT2 when using the Output Compare
channel, independently of whether the Timer/Counter is running or not. If the value written to
TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect wave-
149
8160C–AVR–07/09
ATMEL [ ATMEL ]
