ATmega169P
Table 24-3 summaries the scan registers for the external clock pin XTAL1, oscillators with
XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Table 24-3. Scan Signals for the Oscillator(1)(2)(3)
Scanned
Clock Line
Scanned Clock Line
when not Used
Enable Signal
Clock Option
EXTCLKEN
EXTCLK (XTAL1)
External Clock
0
1
1
External Crystal
OSCON
OSCCK
External Ceramic Resonator
OSC32EN
OSC32CK
Low Freq. External Crystal
Notes: 1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided.
24.5.4
Scanning the Analog Comparator
The relevant Comparator signals regarding Boundary-scan are shown in Figure 24-7. The
Boundary-scan cell from Figure 24-8 is attached to each of these signals. The signals are
described in Table 24-4.
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Figure 24-7. Analog Comparator
BANDGAP
REFERENCE
ACBG
ACD
ACO
AC_IDLE
ACME
ADCEN
ADC MULTIPLEXER
OUTPUT
265
8018A–AVR–03/06
ATMEL [ ATMEL ]
